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![Masahiro Yamada](/assets/img/avatar_default.png)
The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
433 lines
11 KiB
C
433 lines
11 KiB
C
/*
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* TNETV107X: Clock management APIs
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm-generic/errno.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/clock.h>
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#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE
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#define PSC_BASE TNETV107X_PSC_BASE
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#define BIT(x) (1 << (x))
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#define MAX_PREDIV 64
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#define MAX_POSTDIV 8
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#define MAX_MULT 512
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#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
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/* LPSC registers */
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#define PSC_PTCMD 0x120
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#define PSC_PTSTAT 0x128
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#define PSC_MDSTAT(n) (0x800 + (n) * 4)
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#define PSC_MDCTL(n) (0xA00 + (n) * 4)
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#define PSC_MDCTL_LRSTZ BIT(8)
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#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg)))
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#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
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/* SSPLL registers */
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struct sspll_regs {
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u32 modes;
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u32 postdiv;
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u32 prediv;
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u32 mult_factor;
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u32 divider_range;
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u32 bw_divider;
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u32 spr_amount;
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u32 spr_rate_div;
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u32 diag;
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};
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/* SSPLL base addresses */
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static struct sspll_regs *sspll_regs[] = {
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(struct sspll_regs *)(CLOCK_BASE + 0x040),
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(struct sspll_regs *)(CLOCK_BASE + 0x080),
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(struct sspll_regs *)(CLOCK_BASE + 0x0c0),
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};
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#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg))
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#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg))
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#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
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/* PLL Control Registers */
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struct pllctl_regs {
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u32 ctl; /* 00 */
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u32 ocsel; /* 04 */
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u32 secctl; /* 08 */
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u32 __pad0;
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u32 mult; /* 10 */
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u32 prediv; /* 14 */
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u32 div1; /* 18 */
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u32 div2; /* 1c */
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u32 div3; /* 20 */
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u32 oscdiv1; /* 24 */
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u32 postdiv; /* 28 */
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u32 bpdiv; /* 2c */
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u32 wakeup; /* 30 */
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u32 __pad1;
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u32 cmd; /* 38 */
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u32 stat; /* 3c */
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u32 alnctl; /* 40 */
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u32 dchange; /* 44 */
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u32 cken; /* 48 */
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u32 ckstat; /* 4c */
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u32 systat; /* 50 */
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u32 ckctl; /* 54 */
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u32 __pad2[2];
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u32 div4; /* 60 */
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u32 div5; /* 64 */
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u32 div6; /* 68 */
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u32 div7; /* 6c */
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u32 div8; /* 70 */
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};
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struct lpsc_map {
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int pll, div;
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};
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static struct pllctl_regs *pllctl_regs[] = {
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(struct pllctl_regs *)(CLOCK_BASE + 0x700),
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(struct pllctl_regs *)(CLOCK_BASE + 0x300),
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(struct pllctl_regs *)(CLOCK_BASE + 0x500),
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};
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#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
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#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
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#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
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#define pllctl_reg_rmw(pll, reg, mask, val) \
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pllctl_reg_write(pll, reg, \
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(pllctl_reg_read(pll, reg) & ~(mask)) | val)
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#define pllctl_reg_setbits(pll, reg, mask) \
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pllctl_reg_rmw(pll, reg, 0, mask)
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#define pllctl_reg_clrbits(pll, reg, mask) \
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pllctl_reg_rmw(pll, reg, mask, 0)
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/* PLLCTL Bits */
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#define PLLCTL_CLKMODE BIT(8)
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#define PLLCTL_PLLSELB BIT(7)
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#define PLLCTL_PLLENSRC BIT(5)
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#define PLLCTL_PLLDIS BIT(4)
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#define PLLCTL_PLLRST BIT(3)
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#define PLLCTL_PLLPWRDN BIT(1)
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#define PLLCTL_PLLEN BIT(0)
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#define PLLDIV_ENABLE BIT(15)
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static int pll_div_offset[] = {
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#define div_offset(reg) offsetof(struct pllctl_regs, reg)
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div_offset(div1), div_offset(div2), div_offset(div3),
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div_offset(div4), div_offset(div5), div_offset(div6),
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div_offset(div7), div_offset(div8),
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};
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static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
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static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
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/* Mappings from PLL+DIV to subsystem clocks */
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#define sys_arm1176_clk {SYS_PLL, 0}
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#define sys_dsp_clk {SYS_PLL, 1}
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#define sys_ddr_clk {SYS_PLL, 2}
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#define sys_full_clk {SYS_PLL, 3}
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#define sys_lcd_clk {SYS_PLL, 4}
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#define sys_vlynq_ref_clk {SYS_PLL, 5}
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#define sys_tsc_clk {SYS_PLL, 6}
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#define sys_half_clk {SYS_PLL, 7}
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#define eth_clk_5 {ETH_PLL, 0}
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#define eth_clk_50 {ETH_PLL, 1}
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#define eth_clk_125 {ETH_PLL, 2}
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#define eth_clk_250 {ETH_PLL, 3}
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#define eth_clk_25 {ETH_PLL, 4}
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#define tdm_clk {TDM_PLL, 0}
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#define tdm_extra_clk {TDM_PLL, 1}
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#define tdm1_clk {TDM_PLL, 2}
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static const struct lpsc_map lpsc_clk_map[] = {
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[TNETV107X_LPSC_ARM] = sys_arm1176_clk,
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[TNETV107X_LPSC_GEM] = sys_dsp_clk,
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[TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk,
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[TNETV107X_LPSC_TPCC] = sys_full_clk,
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[TNETV107X_LPSC_TPTC0] = sys_full_clk,
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[TNETV107X_LPSC_TPTC1] = sys_full_clk,
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[TNETV107X_LPSC_RAM] = sys_full_clk,
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[TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk,
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[TNETV107X_LPSC_LCD] = sys_lcd_clk,
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[TNETV107X_LPSC_ETHSS] = eth_clk_125,
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[TNETV107X_LPSC_AEMIF] = sys_full_clk,
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[TNETV107X_LPSC_CHIP_CFG] = sys_half_clk,
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[TNETV107X_LPSC_TSC] = sys_tsc_clk,
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[TNETV107X_LPSC_ROM] = sys_half_clk,
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[TNETV107X_LPSC_UART2] = sys_half_clk,
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[TNETV107X_LPSC_PKTSEC] = sys_half_clk,
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[TNETV107X_LPSC_SECCTL] = sys_half_clk,
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[TNETV107X_LPSC_KEYMGR] = sys_half_clk,
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[TNETV107X_LPSC_KEYPAD] = sys_half_clk,
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[TNETV107X_LPSC_GPIO] = sys_half_clk,
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[TNETV107X_LPSC_MDIO] = sys_half_clk,
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[TNETV107X_LPSC_SDIO0] = sys_half_clk,
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[TNETV107X_LPSC_UART0] = sys_half_clk,
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[TNETV107X_LPSC_UART1] = sys_half_clk,
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[TNETV107X_LPSC_TIMER0] = sys_half_clk,
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[TNETV107X_LPSC_TIMER1] = sys_half_clk,
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[TNETV107X_LPSC_WDT_ARM] = sys_half_clk,
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[TNETV107X_LPSC_WDT_DSP] = sys_half_clk,
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[TNETV107X_LPSC_SSP] = sys_half_clk,
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[TNETV107X_LPSC_TDM0] = tdm_clk,
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[TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk,
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[TNETV107X_LPSC_MCDMA] = sys_half_clk,
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[TNETV107X_LPSC_USB0] = sys_half_clk,
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[TNETV107X_LPSC_TDM1] = tdm1_clk,
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[TNETV107X_LPSC_DEBUGSS] = sys_half_clk,
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[TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250,
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[TNETV107X_LPSC_SYSTEM] = sys_half_clk,
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[TNETV107X_LPSC_IMCOP] = sys_dsp_clk,
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[TNETV107X_LPSC_SPARE] = sys_half_clk,
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[TNETV107X_LPSC_SDIO1] = sys_half_clk,
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[TNETV107X_LPSC_USB1] = sys_half_clk,
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[TNETV107X_LPSC_USBSS] = sys_half_clk,
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[TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk,
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[TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk,
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};
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static const unsigned long pll_ext_freq[] = {
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[SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
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[ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
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[TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
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};
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static unsigned long pll_freq_get(int pll)
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{
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unsigned long mult = 1, prediv = 1, postdiv = 1;
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unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
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unsigned long ret;
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u32 bypass;
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bypass = __raw_readl((u32 *)(CLOCK_BASE));
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if (!(bypass & pll_bypass_mask[pll])) {
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mult = sspll_reg_read(pll, mult_factor);
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prediv = sspll_reg_read(pll, prediv) + 1;
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postdiv = sspll_reg_read(pll, postdiv) + 1;
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}
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if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
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ref = pll_ext_freq[pll];
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if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
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return ref;
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ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
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ret /= (prediv * postdiv);
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return ret;
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}
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static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
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int div)
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{
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int divider = 1;
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unsigned long divreg;
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divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
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if (divreg & PLLDIV_ENABLE)
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divider = (divreg & pll_div_mask[pll]) + 1;
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return fpll / divider;
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}
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static unsigned long pll_div_freq_get(int pll, int div)
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{
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unsigned int fpll = pll_freq_get(pll);
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return __pll_div_freq_get(pll, fpll, div);
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}
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static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
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unsigned long hz)
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{
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int divider = (fpll / hz - 1);
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divider &= pll_div_mask[pll];
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divider |= PLLDIV_ENABLE;
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__raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
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pllctl_reg_setbits(pll, alnctl, (1 << div));
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pllctl_reg_setbits(pll, dchange, (1 << div));
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}
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static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
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{
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unsigned int fpll = pll_freq_get(pll);
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__pll_div_freq_set(pll, fpll, div, hz);
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pllctl_reg_write(pll, cmd, 1);
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/* Wait until new divider takes effect */
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while (pllctl_reg_read(pll, stat) & 0x01);
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return __pll_div_freq_get(pll, fpll, div);
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}
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unsigned long clk_get_rate(unsigned int clk)
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{
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return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
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}
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unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
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{
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unsigned long fpll, divider, pll;
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pll = lpsc_clk_map[clk].pll;
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fpll = pll_freq_get(pll);
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divider = (fpll / hz - 1);
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divider &= pll_div_mask[pll];
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return fpll / (divider + 1);
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}
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int clk_set_rate(unsigned int clk, unsigned long _hz)
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{
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unsigned long hz;
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hz = clk_round_rate(clk, _hz);
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if (hz != _hz)
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return -EINVAL; /* Cannot set to target freq */
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pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
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return 0;
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}
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void lpsc_control(int mod, unsigned long state, int lrstz)
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{
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u32 mdctl;
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mdctl = psc_reg_read(PSC_MDCTL(mod));
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mdctl &= ~0x1f;
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mdctl |= state;
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if (lrstz == 0)
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mdctl &= ~PSC_MDCTL_LRSTZ;
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else if (lrstz == 1)
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mdctl |= PSC_MDCTL_LRSTZ;
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psc_reg_write(PSC_MDCTL(mod), mdctl);
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psc_reg_write(PSC_PTCMD, 1);
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/* wait for power domain transition to end */
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while (psc_reg_read(PSC_PTSTAT) & 1);
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/* Wait for module state change */
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while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
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}
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int lpsc_status(unsigned int id)
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{
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return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
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}
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static void init_pll(const struct pll_init_data *data)
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{
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unsigned long fpll;
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unsigned long best_pre = 0, best_post = 0, best_mult = 0;
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unsigned long div, prediv, postdiv, mult;
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unsigned long delta, actual;
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long best_delta = -1;
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int i;
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u32 tmp;
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if (data->pll == SYS_PLL)
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return; /* cannot reconfigure system pll on the fly */
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tmp = pllctl_reg_read(data->pll, ctl);
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if (data->internal_osc) {
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tmp &= ~PLLCTL_CLKMODE;
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fpll = CONFIG_SYS_INT_OSC_FREQ;
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} else {
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tmp |= PLLCTL_CLKMODE;
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fpll = pll_ext_freq[data->pll];
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}
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pllctl_reg_write(data->pll, ctl, tmp);
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mult = data->pll_freq / fpll;
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for (mult = max(mult, 1); mult <= MAX_MULT; mult++) {
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div = (fpll * mult) / data->pll_freq;
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if (div < 1 || div > MAX_DIV)
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continue;
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for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
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prediv = div / postdiv;
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if (prediv < 1 || prediv > MAX_PREDIV)
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continue;
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actual = (fpll / prediv) * (mult / postdiv);
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delta = (actual - data->pll_freq);
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if (delta < 0)
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delta = -delta;
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if ((delta < best_delta) || (best_delta == -1)) {
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best_delta = delta;
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best_mult = mult;
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best_pre = prediv;
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best_post = postdiv;
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if (delta == 0)
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goto done;
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}
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}
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}
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done:
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if (best_delta == -1) {
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printf("pll cannot derive %lu from %lu\n",
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data->pll_freq, fpll);
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return;
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}
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fpll = fpll * best_mult;
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fpll /= best_pre * best_post;
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
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pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
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sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
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sspll_reg_write(data->pll, prediv, best_pre - 1);
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sspll_reg_write(data->pll, postdiv, best_post - 1);
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for (i = 0; i < 10; i++)
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if (data->div_freq[i])
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__pll_div_freq_set(data->pll, fpll, i,
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data->div_freq[i]);
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pllctl_reg_write(data->pll, cmd, 1);
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/* Wait until pll "go" operation completes */
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while (pllctl_reg_read(data->pll, stat) & 0x01);
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
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pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
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}
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void init_plls(int num_pll, struct pll_init_data *config)
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{
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int i;
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for (i = 0; i < num_pll; i++)
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init_pll(&config[i]);
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}
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