mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
3db86f4bbd
As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
77 lines
1.3 KiB
ArmAsm
77 lines
1.3 KiB
ArmAsm
/*
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* Copyright 2016 NXP Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/system.h>
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#include <asm/macro.h>
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WEAK(_sec_firmware_entry)
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/*
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* x0: Secure Firmware entry point
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* x1: Exception return address Low
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* x2: Exception return address High
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*/
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/* Save stack pointer for EL2 */
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mov x3, sp
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msr sp_el2, x3
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/* Set exception return address hold pointer */
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adr x4, 1f
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mov x3, x4
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#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT
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rev w3, w3
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#endif
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str w3, [x1]
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lsr x3, x4, #32
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#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT
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rev w3, w3
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#endif
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str w3, [x2]
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/* Call SEC monitor */
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br x0
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1:
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mov x0, #0
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ret
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ENDPROC(_sec_firmware_entry)
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#ifdef CONFIG_ARMV8_PSCI
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ENTRY(_sec_firmware_support_psci_version)
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mov x0, 0x84000000
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mov x1, 0x0
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mov x2, 0x0
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mov x3, 0x0
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smc #0
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ret
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ENDPROC(_sec_firmware_support_psci_version)
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/*
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* Switch from AArch64 EL2 to AArch32 EL2
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* @param inputs:
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* x0: argument, zero
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* x1: machine nr
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* x2: fdt address
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* x3: kernel entry point
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* @param outputs for secure firmware:
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* x0: function id
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* x1: kernel entry point
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* x2: machine nr
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* x3: fdt address
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*/
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ENTRY(armv8_el2_to_aarch32)
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mov x0, x3
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mov x3, x2
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mov x2, x1
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mov x1, x0
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ldr x0, =0xc000ff04
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smc #0
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ret
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ENDPROC(armv8_el2_to_aarch32)
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#endif
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