mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
446 lines
9.9 KiB
ArmAsm
446 lines
9.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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.macro or32, addr, data
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mov.l \addr, r1
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mov.l \data, r0
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mov.l @r1, r2
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or r2, r0
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mov.l r0, @r1
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.endm
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.macro wait_DBCMD
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mov.l DBWAIT_A, r0
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mov.l @r0, r1
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.endm
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.global lowlevel_init
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.section .spiboot1.text
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.align 2
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lowlevel_init:
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/*------- GPIO -------*/
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write16 PDCR_A, PDCR_D ! SPI0
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write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1)
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write16 PJCR_A, PJCR_D ! SCIF4
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write16 PTCR_A, PTCR_D ! STATUS
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write16 PSEL1_A, PSEL1_D ! SPI0
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write16 PSEL2_A, PSEL2_D ! SPI0
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write16 PSEL5_A, PSEL5_D ! STATUS
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bra exit_gpio
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nop
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.align 2
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/*------- GPIO -------*/
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PDCR_A: .long 0xffec0006
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PGCR_A: .long 0xffec000c
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PJCR_A: .long 0xffec0012
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PTCR_A: .long 0xffec0026
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PSEL1_A: .long 0xffec0072
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PSEL2_A: .long 0xffec0074
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PSEL5_A: .long 0xffec007a
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PDCR_D: .long 0x0000
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PGCR_D: .long 0x0004
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PJCR_D: .long 0x0000
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PTCR_D: .long 0x0000
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PSEL1_D: .long 0x0000
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PSEL2_D: .long 0x3000
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PSEL5_D: .long 0x0ffc
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.align 2
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exit_gpio:
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mov #0, r14
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mova 2f, r0
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mov.l PC_MASK, r1
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tst r0, r1
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bf 2f
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bra exit_pmb
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nop
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.align 2
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/* If CPU runs on SDRAM (PC=0x5???????) or not. */
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PC_MASK: .long 0x20000000
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2:
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mov #1, r14
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mov.l EXPEVT_A, r0
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mov.l @r0, r0
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mov.l EXPEVT_POWER_ON_RESET, r1
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cmp/eq r0, r1
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bt 1f
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/*
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* If EXPEVT value is manual reset or tlb multipul-hit,
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* initialization of DDR3IF is not necessary.
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*/
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bra exit_ddr
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nop
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1:
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/*------- Reset -------*/
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write32 MRSTCR0_A, MRSTCR0_D
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write32 MRSTCR1_A, MRSTCR1_D
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/* For Core Reset */
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mov.l DBACEN_A, r0
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mov.l @r0, r0
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cmp/eq #0, r0
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bt 3f
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/*
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* If DBACEN == 1(DBSC was already enabled), we have to avoid the
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* initialization of DDR3-SDRAM.
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*/
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bra exit_ddr
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nop
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3:
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/*------- DDR3IF -------*/
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/* oscillation stabilization time */
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wait_timer WAIT_OSC_TIME
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/* step 3 */
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write32 DBCMD_A, DBCMD_RSTL_VAL
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wait_timer WAIT_30US
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/* step 4 */
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write32 DBCMD_A, DBCMD_PDEN_VAL
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/* step 5 */
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write32 DBKIND_A, DBKIND_D
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/* step 6 */
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write32 DBCONF_A, DBCONF_D
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write32 DBTR0_A, DBTR0_D
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write32 DBTR1_A, DBTR1_D
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write32 DBTR2_A, DBTR2_D
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write32 DBTR3_A, DBTR3_D
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write32 DBTR4_A, DBTR4_D
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write32 DBTR5_A, DBTR5_D
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write32 DBTR6_A, DBTR6_D
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write32 DBTR7_A, DBTR7_D
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write32 DBTR8_A, DBTR8_D
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write32 DBTR9_A, DBTR9_D
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write32 DBTR10_A, DBTR10_D
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write32 DBTR11_A, DBTR11_D
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write32 DBTR12_A, DBTR12_D
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write32 DBTR13_A, DBTR13_D
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write32 DBTR14_A, DBTR14_D
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write32 DBTR15_A, DBTR15_D
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write32 DBTR16_A, DBTR16_D
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write32 DBTR17_A, DBTR17_D
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write32 DBTR18_A, DBTR18_D
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write32 DBTR19_A, DBTR19_D
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write32 DBRNK0_A, DBRNK0_D
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/* step 7 */
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write32 DBPDCNT3_A, DBPDCNT3_D
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/* step 8 */
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write32 DBPDCNT1_A, DBPDCNT1_D
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write32 DBPDCNT2_A, DBPDCNT2_D
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write32 DBPDLCK_A, DBPDLCK_D
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write32 DBPDRGA_A, DBPDRGA_D
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write32 DBPDRGD_A, DBPDRGD_D
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/* step 9 */
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wait_timer WAIT_30US
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/* step 10 */
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write32 DBPDCNT0_A, DBPDCNT0_D
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/* step 11 */
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wait_timer WAIT_30US
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wait_timer WAIT_30US
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/* step 12 */
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write32 DBCMD_A, DBCMD_WAIT_VAL
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wait_DBCMD
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/* step 13 */
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write32 DBCMD_A, DBCMD_RSTH_VAL
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wait_DBCMD
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/* step 14 */
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write32 DBCMD_A, DBCMD_WAIT_VAL
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write32 DBCMD_A, DBCMD_WAIT_VAL
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write32 DBCMD_A, DBCMD_WAIT_VAL
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write32 DBCMD_A, DBCMD_WAIT_VAL
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/* step 15 */
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write32 DBCMD_A, DBCMD_PDXT_VAL
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/* step 16 */
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write32 DBCMD_A, DBCMD_MRS2_VAL
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/* step 17 */
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write32 DBCMD_A, DBCMD_MRS3_VAL
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/* step 18 */
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write32 DBCMD_A, DBCMD_MRS1_VAL
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/* step 19 */
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write32 DBCMD_A, DBCMD_MRS0_VAL
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/* step 20 */
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write32 DBCMD_A, DBCMD_ZQCL_VAL
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write32 DBCMD_A, DBCMD_REF_VAL
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write32 DBCMD_A, DBCMD_REF_VAL
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wait_DBCMD
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/* step 21 */
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write32 DBADJ0_A, DBADJ0_D
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write32 DBADJ1_A, DBADJ1_D
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write32 DBADJ2_A, DBADJ2_D
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/* step 22 */
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write32 DBRFCNF0_A, DBRFCNF0_D
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write32 DBRFCNF1_A, DBRFCNF1_D
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write32 DBRFCNF2_A, DBRFCNF2_D
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/* step 23 */
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write32 DBCALCNF_A, DBCALCNF_D
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/* step 24 */
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write32 DBRFEN_A, DBRFEN_D
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write32 DBCMD_A, DBCMD_SRXT_VAL
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/* step 25 */
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write32 DBACEN_A, DBACEN_D
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/* step 26 */
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wait_DBCMD
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bra exit_ddr
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nop
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.align 2
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EXPEVT_A: .long 0xff000024
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EXPEVT_POWER_ON_RESET: .long 0x00000000
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/*------- Reset -------*/
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MRSTCR0_A: .long 0xffd50030
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MRSTCR0_D: .long 0xfe1ffe7f
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MRSTCR1_A: .long 0xffd50034
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MRSTCR1_D: .long 0xfff3ffff
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/*------- DDR3IF -------*/
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DBCMD_A: .long 0xfe800018
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DBKIND_A: .long 0xfe800020
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DBCONF_A: .long 0xfe800024
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DBTR0_A: .long 0xfe800040
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DBTR1_A: .long 0xfe800044
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DBTR2_A: .long 0xfe800048
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DBTR3_A: .long 0xfe800050
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DBTR4_A: .long 0xfe800054
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DBTR5_A: .long 0xfe800058
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DBTR6_A: .long 0xfe80005c
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DBTR7_A: .long 0xfe800060
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DBTR8_A: .long 0xfe800064
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DBTR9_A: .long 0xfe800068
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DBTR10_A: .long 0xfe80006c
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DBTR11_A: .long 0xfe800070
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DBTR12_A: .long 0xfe800074
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DBTR13_A: .long 0xfe800078
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DBTR14_A: .long 0xfe80007c
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DBTR15_A: .long 0xfe800080
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DBTR16_A: .long 0xfe800084
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DBTR17_A: .long 0xfe800088
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DBTR18_A: .long 0xfe80008c
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DBTR19_A: .long 0xfe800090
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DBRNK0_A: .long 0xfe800100
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DBPDCNT0_A: .long 0xfe800200
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DBPDCNT1_A: .long 0xfe800204
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DBPDCNT2_A: .long 0xfe800208
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DBPDCNT3_A: .long 0xfe80020c
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DBPDLCK_A: .long 0xfe800280
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DBPDRGA_A: .long 0xfe800290
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DBPDRGD_A: .long 0xfe8002a0
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DBADJ0_A: .long 0xfe8000c0
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DBADJ1_A: .long 0xfe8000c4
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DBADJ2_A: .long 0xfe8000c8
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DBRFCNF0_A: .long 0xfe8000e0
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DBRFCNF1_A: .long 0xfe8000e4
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DBRFCNF2_A: .long 0xfe8000e8
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DBCALCNF_A: .long 0xfe8000f4
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DBRFEN_A: .long 0xfe800014
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DBACEN_A: .long 0xfe800010
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DBWAIT_A: .long 0xfe80001c
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WAIT_OSC_TIME: .long 6000
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WAIT_30US: .long 13333
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DBCMD_RSTL_VAL: .long 0x20000000
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DBCMD_PDEN_VAL: .long 0x1000d73c
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DBCMD_WAIT_VAL: .long 0x0000d73c
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DBCMD_RSTH_VAL: .long 0x2100d73c
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DBCMD_PDXT_VAL: .long 0x110000c8
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DBCMD_MRS0_VAL: .long 0x28000930
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DBCMD_MRS1_VAL: .long 0x29000004
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DBCMD_MRS2_VAL: .long 0x2a000008
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DBCMD_MRS3_VAL: .long 0x2b000000
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DBCMD_ZQCL_VAL: .long 0x03000200
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DBCMD_REF_VAL: .long 0x0c000000
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DBCMD_SRXT_VAL: .long 0x19000000
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DBKIND_D: .long 0x00000007
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DBCONF_D: .long 0x0f030a01
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DBTR0_D: .long 0x00000007
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DBTR1_D: .long 0x00000006
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DBTR2_D: .long 0x00000000
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DBTR3_D: .long 0x00000007
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DBTR4_D: .long 0x00070007
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DBTR5_D: .long 0x0000001b
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DBTR6_D: .long 0x00000014
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DBTR7_D: .long 0x00000005
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DBTR8_D: .long 0x00000015
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DBTR9_D: .long 0x00000006
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DBTR10_D: .long 0x00000008
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DBTR11_D: .long 0x00000007
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DBTR12_D: .long 0x0000000e
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DBTR13_D: .long 0x00000056
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DBTR14_D: .long 0x00000006
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DBTR15_D: .long 0x00000004
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DBTR16_D: .long 0x00150002
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DBTR17_D: .long 0x000c0017
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DBTR18_D: .long 0x00000200
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DBTR19_D: .long 0x00000040
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DBRNK0_D: .long 0x00000001
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DBPDCNT0_D: .long 0x00000001
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DBPDCNT1_D: .long 0x00000001
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DBPDCNT2_D: .long 0x00000000
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DBPDCNT3_D: .long 0x00004010
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DBPDLCK_D: .long 0x0000a55a
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DBPDRGA_D: .long 0x00000028
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DBPDRGD_D: .long 0x00017100
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DBADJ0_D: .long 0x00000000
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DBADJ1_D: .long 0x00000000
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DBADJ2_D: .long 0x18061806
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DBRFCNF0_D: .long 0x000001ff
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DBRFCNF1_D: .long 0x08001000
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DBRFCNF2_D: .long 0x00000000
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DBCALCNF_D: .long 0x0000ffff
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DBRFEN_D: .long 0x00000001
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DBACEN_D: .long 0x00000001
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.align 2
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exit_ddr:
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#if defined(CONFIG_SH_32BIT)
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/*------- set PMB -------*/
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write32 PASCR_A, PASCR_29BIT_D
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write32 MMUCR_A, MMUCR_D
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/*****************************************************************
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* ent virt phys v sz c wt
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* 0 0xa0000000 0x00000000 1 128M 0 1
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* 1 0xa8000000 0x48000000 1 128M 0 1
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* 5 0x88000000 0x48000000 1 128M 1 1
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*/
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write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
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write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
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write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
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write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
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write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
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write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
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write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
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write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
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write32 PASCR_A, PASCR_INIT
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mov.l DUMMY_ADDR, r0
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icbi @r0
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#endif /* if defined(CONFIG_SH_32BIT) */
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exit_pmb:
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/* CPU is running on ILRAM? */
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mov r14, r0
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tst #1, r0
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bt 1f
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mov.l _stack_ilram, r15
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mov.l _spiboot_main, r0
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100: bsrf r0
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nop
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.align 2
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_spiboot_main: .long (spiboot_main - (100b + 4))
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_stack_ilram: .long 0xe5204000
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1:
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write32 CCR_A, CCR_D
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rts
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nop
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.align 2
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#if defined(CONFIG_SH_32BIT)
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/*------- set PMB -------*/
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PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
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PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
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PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
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PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
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PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
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PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
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PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
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PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
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PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
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PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
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PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
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PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
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PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
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PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
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PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
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PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
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PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
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PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
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PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
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PMB_ADDR_NOT_USE_D: .long 0x00000000
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PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
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PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
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PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
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/* ppn ub v s1 s0 c wt */
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PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
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PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
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PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
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PASCR_A: .long 0xff000070
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DUMMY_ADDR: .long 0xa0000000
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PASCR_29BIT_D: .long 0x00000000
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PASCR_INIT: .long 0x80000080
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MMUCR_A: .long 0xff000010
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MMUCR_D: .long 0x00000004 /* clear ITLB */
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#endif /* CONFIG_SH_32BIT */
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CCR_A: .long CCR
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CCR_D: .long CCR_CACHE_INIT
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