mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 05:36:17 +09:00
fa2f81b06f
On all TI platforms the ROM defines a "downloaded image" area at or near the start of SRAM which is followed by a reserved area. As it is at best bad form and at worst possibly harmful in corner cases to write in this reserved area, we stop doing that by adding in the define NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this. At current we define the end of scratch space at 0x228 bytes past the start of scratch space this this gives us a lot of room to grow. As these scratch uses are non-optional today, all targets are modified to respect this boundary. Tested on OMAP4 Pandaboard, OMAP3 Beagle xM Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Paul Kocialkowski <contact@paulk.fr> Cc: Enric Balletbo i Serra <eballetbo@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Thomas Weber <weber@corscience.de> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Heiko Schocher <hs@denx.de> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: "B, Ravi" <ravibabu@ti.com> Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: "Kipisz, Steven" <s-kipisz2@ti.com> Cc: Daniel Allred <d-allred@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Ladislav Michl <ladis@linux-mips.org>
177 lines
4.9 KiB
C
177 lines
4.9 KiB
C
/*
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* (C) Copyright 2013
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* Texas Instruments Incorporated.
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* Sricharan R <r.sricharan@ti.com>
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*
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* Derived from OMAP4 done by:
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* Aneesh V <aneesh@ti.com>
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*
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* TI OMAP5 AND DRA7XX common configuration settings
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* For more details, please see the technical documents listed at
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* http://www.ti.com/product/omap5432
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*/
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#ifndef __CONFIG_TI_OMAP5_COMMON_H
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#define __CONFIG_TI_OMAP5_COMMON_H
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Common ARM Erratas */
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#define CONFIG_ARM_ERRATA_798870
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/* Use General purpose timer 1 */
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#define CONFIG_SYS_TIMERBASE GPT2_BASE
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/*
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* For the DDR timing information we can either dynamically determine
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* the timings to use or use pre-determined timings (based on using the
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* dynamic method. Default to the static timing infomation.
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*/
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#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
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#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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#endif
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#define CONFIG_PALMAS_POWER
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#include <asm/arch/cpu.h>
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#include <asm/arch/omap.h>
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#include <configs/ti_armv7_omap.h>
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/*
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* Hardware drivers
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*/
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#define CONFIG_SYS_NS16550_CLK 48000000
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#endif
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/*
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* Environment setup
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*/
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#ifndef PARTS_DEFAULT
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#define PARTS_DEFAULT
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#endif
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#ifndef DFUARGS
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#define DFUARGS
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#endif
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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#define CONFIG_EXTRA_ENV_SETTINGS \
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DEFAULT_LINUX_BOOT_ENV \
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DEFAULT_MMC_TI_ARGS \
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"console=" CONSOLEDEV ",115200n8\0" \
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"fdtfile=undefined\0" \
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"bootpart=0:2\0" \
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"bootdir=/boot\0" \
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"bootfile=zImage\0" \
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"usbtty=cdc_acm\0" \
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"vram=16M\0" \
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"partitions=" PARTS_DEFAULT "\0" \
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"optargs=\0" \
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"dofastboot=0\0" \
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"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
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"source ${loadaddr}\0" \
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"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
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"mmcboot=mmc dev ${mmcdev}; " \
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"if mmc rescan; then " \
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"echo SD/MMC found on device ${mmcdev};" \
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"if run loadimage; then " \
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"run loadfdt; " \
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"echo Booting from mmc${mmcdev} ...; " \
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"run args_mmc; " \
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"bootz ${loadaddr} - ${fdtaddr}; " \
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"fi;" \
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"fi;\0" \
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"findfdt="\
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"if test $board_name = omap5_uevm; then " \
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"setenv fdtfile omap5-uevm.dtb; fi; " \
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"if test $board_name = dra7xx; then " \
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"setenv fdtfile dra7-evm.dtb; fi;" \
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"if test $board_name = dra72x-revc; then " \
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"setenv fdtfile dra72-evm-revc.dtb; fi;" \
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"if test $board_name = dra72x; then " \
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"setenv fdtfile dra72-evm.dtb; fi;" \
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"if test $board_name = beagle_x15; then " \
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"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
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"if test $board_name = am572x_idk; then " \
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"setenv fdtfile am572x-idk.dtb; fi;" \
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"if test $board_name = am57xx_evm; then " \
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"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
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"if test $fdtfile = undefined; then " \
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"echo WARNING: Could not determine device tree to use; fi; \0" \
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"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
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DFUARGS \
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NETARGS \
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#define CONFIG_BOOTCOMMAND \
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"if test ${dofastboot} -eq 1; then " \
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"echo Boot fastboot requested, resetting dofastboot ...;" \
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"setenv dofastboot 0; saveenv;" \
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"echo Booting into fastboot ...; fastboot 0;" \
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"fi;" \
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"run findfdt; " \
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"run envboot; " \
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"run mmcboot;" \
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"setenv mmcdev 1; " \
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"setenv bootpart 1:2; " \
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"setenv mmcroot /dev/mmcblk0p2 rw; " \
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"run mmcboot;" \
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""
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#endif
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/*
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* SPL related defines. The Public RAM memory map the ROM defines the
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* area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
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* On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
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* We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
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* print some information.
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*/
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#ifdef CONFIG_TI_SECURE_DEVICE
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/*
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* For memory booting on HS parts, the first 4KB of the internal RAM is
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* reserved for secure world use and the flash loader image is
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* preceded by a secure certificate. The SPL will therefore run in internal
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* RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
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*/
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#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
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#define CONFIG_SPL_TEXT_BASE 0x40301350
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#else
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/*
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* For all booting on GP parts, the flash loader image is
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* downloaded into internal RAM at address 0x40300000.
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*/
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#define CONFIG_SPL_TEXT_BASE 0x40300000
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#endif
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#define CONFIG_SPL_DISPLAY_PRINT
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
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(128 << 20))
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#ifdef CONFIG_NAND
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#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
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#endif
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/*
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* Disable MMC DM for SPL build and can be re-enabled after adding
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* DM support in SPL
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*/
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#ifdef CONFIG_SPL_BUILD
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#undef CONFIG_DM_MMC
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#undef CONFIG_TIMER
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#undef CONFIG_DM_ETH
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#endif
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#endif /* __CONFIG_TI_OMAP5_COMMON_H */
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