mirror of
https://github.com/brain-hackers/u-boot-brain
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615e9b3cce
Let's use rockchip timer before stimer patches can be merged. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
70 lines
1.1 KiB
Plaintext
70 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
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*/
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/ {
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chosen {
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u-boot,spl-boot-order = &emmc;
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tick-timer = "/timer@ff810000";
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};
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};
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&dmc {
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u-boot,dm-pre-reloc;
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/*
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* PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
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* See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
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* details on the 'rockchip,memory-schedule' property and how it
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* affects the physical-address to device-address mapping.
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*/
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rockchip,memory-schedule = <DMC_MSCH_CBRD>;
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rockchip,ddr-frequency = <800000000>;
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rockchip,ddr-speed-bin = <DDR3_1600K>;
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status = "okay";
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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};
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&service_msch {
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u-boot,dm-pre-reloc;
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};
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&dmc {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&pmugrf {
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u-boot,dm-pre-reloc;
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};
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&sgrf {
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u-boot,dm-pre-reloc;
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};
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&cru {
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u-boot,dm-pre-reloc;
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};
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&grf {
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u-boot,dm-pre-reloc;
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};
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&uart4 {
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u-boot,dm-pre-reloc;
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};
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&emmc {
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u-boot,dm-pre-reloc;
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};
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&timer0 {
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u-boot,dm-pre-reloc;
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clock-frequency = <24000000>;
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status = "okay";
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};
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