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https://github.com/brain-hackers/u-boot-brain
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f5bd13ed57
On linux kernel side, on STM32F7 and STM32H7 SoCs, DMA requires uncachable regions. These regions are defined in DT. Since kernel linux v4.15, on ARMv7-M Cortex, kernel is able to configure MPU regions depending on DT settings. As kernel is able to configure MPU, this allows to remove MPU region settings in bootloader. On Cortex M processors, MPU allows to use a default memory map. (see B3.5.4 MPU Control Register, MPU_CTRL in https://developer.arm.com/products/architecture/m-profile/docs/ddi0403/latest/armv7-m-architecture-reference-manual) Use the default memory map as background region for all STM32 SoCs family with an additional MPU region corresponding to the SDRAM area. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
85 lines
1.9 KiB
C
85 lines
1.9 KiB
C
/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/bitops.h>
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#include <asm/armv7m.h>
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#include <asm/armv7m_mpu.h>
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#include <asm/io.h>
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#define V7M_MPU_CTRL_ENABLE BIT(0)
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#define V7M_MPU_CTRL_DISABLE (0 << 0)
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#define V7M_MPU_CTRL_HFNMIENA BIT(1)
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#define V7M_MPU_CTRL_PRIVDEFENA BIT(2)
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#define VALID_REGION BIT(4)
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#define ENABLE_REGION BIT(0)
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#define AP_SHIFT 24
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#define XN_SHIFT 28
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#define TEX_SHIFT 19
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#define S_SHIFT 18
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#define C_SHIFT 17
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#define B_SHIFT 16
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#define REGION_SIZE_SHIFT 1
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#define CACHEABLE (1 << C_SHIFT)
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#define BUFFERABLE (1 << B_SHIFT)
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#define SHAREABLE (1 << S_SHIFT)
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void disable_mpu(void)
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{
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writel(0, &V7M_MPU->ctrl);
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}
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void enable_mpu(void)
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{
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writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_PRIVDEFENA, &V7M_MPU->ctrl);
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/* Make sure new mpu config is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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}
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void mpu_config(struct mpu_region_config *reg_config)
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{
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uint32_t attr;
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switch (reg_config->mr_attr) {
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case STRONG_ORDER:
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attr = SHAREABLE;
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break;
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case SHARED_WRITE_BUFFERED:
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attr = BUFFERABLE;
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break;
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case O_I_WT_NO_WR_ALLOC:
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attr = CACHEABLE;
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break;
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case O_I_WB_NO_WR_ALLOC:
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attr = CACHEABLE | BUFFERABLE;
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break;
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case O_I_NON_CACHEABLE:
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attr = 1 << TEX_SHIFT;
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break;
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case O_I_WB_RD_WR_ALLOC:
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attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE;
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break;
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case DEVICE_NON_SHARED:
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attr = (2 << TEX_SHIFT) | BUFFERABLE;
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break;
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default:
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attr = 0; /* strongly ordered */
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break;
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};
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writel(reg_config->start_addr | VALID_REGION | reg_config->region_no,
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&V7M_MPU->rbar);
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writel(reg_config->xn << XN_SHIFT | reg_config->ap << AP_SHIFT | attr
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| reg_config->reg_size << REGION_SIZE_SHIFT | ENABLE_REGION
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, &V7M_MPU->rasr);
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}
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