258 lines
6.4 KiB
C
258 lines
6.4 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/dma.h>
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#include <stdbool.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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struct scu_regs {
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u32 ctrl;
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u32 config;
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u32 status;
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u32 invalidate;
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u32 fpga_rev;
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};
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u32 get_cpu_rev(void)
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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u32 reg = readl(&anatop->digprog_sololite);
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u32 type = ((reg >> 16) & 0xff);
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if (type != MXC_CPU_MX6SL) {
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reg = readl(&anatop->digprog);
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type = ((reg >> 16) & 0xff);
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if (type == MXC_CPU_MX6DL) {
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struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
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u32 cfg = readl(&scu->config) & 3;
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if (!cfg)
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type = MXC_CPU_MX6SOLO;
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}
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}
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reg &= 0xff; /* mx6 silicon revision */
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return (type << 12) | (reg + 0x10);
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}
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#ifdef CONFIG_REVISION_TAG
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u32 __weak get_board_rev(void)
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{
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u32 cpurev = get_cpu_rev();
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u32 type = ((cpurev >> 12) & 0xff);
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if (type == MXC_CPU_MX6SOLO)
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cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
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return cpurev;
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}
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#endif
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void init_aips(void)
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{
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struct aipstz_regs *aips1, *aips2;
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aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
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aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, &aips1->mprot0);
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writel(0x77777777, &aips1->mprot1);
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writel(0x77777777, &aips2->mprot0);
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writel(0x77777777, &aips2->mprot1);
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/*
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* Set all OPACRx to be non-bufferable, not require
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* supervisor privilege level for access,allow for
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* write access and untrusted master access.
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*/
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writel(0x00000000, &aips1->opacr0);
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writel(0x00000000, &aips1->opacr1);
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writel(0x00000000, &aips1->opacr2);
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writel(0x00000000, &aips1->opacr3);
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writel(0x00000000, &aips1->opacr4);
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writel(0x00000000, &aips2->opacr0);
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writel(0x00000000, &aips2->opacr1);
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writel(0x00000000, &aips2->opacr2);
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writel(0x00000000, &aips2->opacr3);
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writel(0x00000000, &aips2->opacr4);
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}
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/*
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* Set the VDDSOC
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*
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* Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
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* them to the specified millivolt level.
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* Possible values are from 0.725V to 1.450V in steps of
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* 0.025V (25mV).
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*/
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void set_vddsoc(u32 mv)
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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u32 val, reg = readl(&anatop->reg_core);
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if (mv < 725)
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val = 0x00; /* Power gated off */
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else if (mv > 1450)
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val = 0x1F; /* Power FET switched full on. No regulation */
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else
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val = (mv - 700) / 25;
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/*
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* Mask out the REG_CORE[22:18] bits (REG2_TRIG)
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* and set them to the calculated value (0.7V + val * 0.25V)
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*/
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reg = (reg & ~(0x1F << 18)) | (val << 18);
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writel(reg, &anatop->reg_core);
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}
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static void imx_set_wdog_powerdown(bool enable)
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{
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struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
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struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
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/* Write to the PDE (Power Down Enable) bit */
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writew(enable, &wdog1->wmcr);
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writew(enable, &wdog2->wmcr);
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}
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int arch_cpu_init(void)
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{
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init_aips();
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set_vddsoc(1200); /* Set VDDSOC to 1.2V */
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imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
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#ifdef CONFIG_APBH_DMA
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/* Start APBH DMA */
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mxs_dma_init();
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#endif
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return 0;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#if defined(CONFIG_FEC_MXC)
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[4];
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struct fuse_bank4_regs *fuse =
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(struct fuse_bank4_regs *)bank->fuse_regs;
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u32 value = readl(&fuse->mac_addr_high);
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mac[0] = (value >> 8);
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mac[1] = value ;
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value = readl(&fuse->mac_addr_low);
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mac[2] = value >> 24 ;
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mac[3] = value >> 16 ;
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mac[4] = value >> 8 ;
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mac[5] = value ;
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}
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#endif
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void boot_mode_apply(unsigned cfg_val)
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{
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unsigned reg;
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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writel(cfg_val, &psrc->gpr9);
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reg = readl(&psrc->gpr10);
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if (cfg_val)
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reg |= 1 << 28;
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else
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reg &= ~(1 << 28);
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writel(reg, &psrc->gpr10);
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}
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/*
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* cfg_val will be used for
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* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
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* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
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* to SBMR1, which will determine the boot device.
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*/
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const struct boot_mode soc_boot_modes[] = {
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{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
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/* reserved value should start rom usb */
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{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
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{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
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{"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
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{"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
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{"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
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{"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
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/* 4 bit bus width */
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{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
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{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
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{"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
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{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
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{NULL, 0},
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};
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void s_init(void)
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{
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}
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#ifdef CONFIG_IMX_HDMI
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void imx_enable_hdmi_phy(void)
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{
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
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u8 reg;
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reg = readb(&hdmi->phy_conf0);
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reg |= HDMI_PHY_CONF0_PDZ_MASK;
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writeb(reg, &hdmi->phy_conf0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
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writeb(reg, &hdmi->phy_conf0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
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writeb(reg, &hdmi->phy_conf0);
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writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
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}
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void imx_setup_hdmi(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
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int reg;
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/* Turn on HDMI PHY clock */
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reg = readl(&mxc_ccm->CCGR2);
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reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
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MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
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writel(reg, &mxc_ccm->CCGR2);
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writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
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reg = readl(&mxc_ccm->chsccdr);
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reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
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MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (CHSCCDR_PODF_DIVIDE_BY_3
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<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
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|(CHSCCDR_IPU_PRE_CLK_540M_PFD
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<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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}
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#endif
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