mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 12:46:17 +09:00
877bfe37dc
This patch introduces the support for Keymile's kmp204x reference design. This design is based on Freescale's P2040/P2041 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - SPI NOR Flash as boot medium - NAND Flash - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt FPGA - 2 HW I2C busses - last but not least, the mandatory serial port The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb support and was changed according to our design (that means essentially removing what is not present on the designs and a few adaptations). There is currently only one prototype board that is based on this design and this patch also introduces it. The board is called kmlion1. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> kmp204x: update the ENV #define The comments had to be refined as well as the total size Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix ddr.c] Acked-by: York Sun <yorksun@freescale.com>
111 lines
3.8 KiB
C
111 lines
3.8 KiB
C
/*
|
|
* (C) Copyright 2013 Keymile AG
|
|
* Valentin Longchamp <valentin.longchamp@keymile.com>
|
|
*
|
|
* Copyright 2008-2011 Freescale Semiconductor, Inc.
|
|
*
|
|
* (C) Copyright 2000
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/mmu.h>
|
|
|
|
struct fsl_e_tlb_entry tlb_table[] = {
|
|
/* TLB 0 - for temp stack in cache */
|
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
|
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
|
|
MAS3_SW|MAS3_SR, 0,
|
|
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
|
|
MAS3_SW|MAS3_SR, 0,
|
|
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
|
|
MAS3_SW|MAS3_SR, 0,
|
|
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
|
|
MAS3_SW|MAS3_SR, 0,
|
|
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
/* TLB 1 */
|
|
/* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
|
|
* SRAM is at 0xfff00000, it covered the 0xfffff000.
|
|
*/
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
|
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 0, BOOKE_PAGESZ_1M, 1),
|
|
|
|
/* *I*G* - CCSRBAR */
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 1, BOOKE_PAGESZ_16M, 1),
|
|
/* QRIO */
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 2, BOOKE_PAGESZ_64K, 1),
|
|
/* *I*G* - PCI1 */
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 3, BOOKE_PAGESZ_512M, 1),
|
|
/* *I*G* - PCI3 */
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 4, BOOKE_PAGESZ_512M, 1),
|
|
/* *I*G* - PCI1&3 I/O */
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 6, BOOKE_PAGESZ_128K, 1),
|
|
#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
|
|
/* LBAPP1 */
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 7, BOOKE_PAGESZ_256M, 1),
|
|
#endif
|
|
#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
|
|
/* LBAPP2 */
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 8, BOOKE_PAGESZ_256M, 1),
|
|
#endif
|
|
/* Bman/Qman */
|
|
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
|
|
MAS3_SW|MAS3_SR, 0,
|
|
0, 9, BOOKE_PAGESZ_1M, 1),
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
|
|
CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 10, BOOKE_PAGESZ_1M, 1),
|
|
#endif
|
|
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
|
|
MAS3_SW|MAS3_SR, 0,
|
|
0, 11, BOOKE_PAGESZ_1M, 1),
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
|
|
CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 12, BOOKE_PAGESZ_1M, 1),
|
|
#endif
|
|
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 13, BOOKE_PAGESZ_4M, 1),
|
|
#endif
|
|
#ifdef CONFIG_SYS_NAND_BASE
|
|
/*
|
|
* *I*G - NAND
|
|
* entry 14 and 15 has been used hard coded, they will be disabled
|
|
* in cpu_init_f, so we use entry 16 for nand.
|
|
*/
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 16, BOOKE_PAGESZ_32K, 1),
|
|
#endif
|
|
};
|
|
|
|
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|