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https://github.com/brain-hackers/u-boot-brain
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877bfe37dc
This patch introduces the support for Keymile's kmp204x reference design. This design is based on Freescale's P2040/P2041 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - SPI NOR Flash as boot medium - NAND Flash - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt FPGA - 2 HW I2C busses - last but not least, the mandatory serial port The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb support and was changed according to our design (that means essentially removing what is not present on the designs and a few adaptations). There is currently only one prototype board that is based on this design and this patch also introduces it. The board is called kmlion1. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> kmp204x: update the ENV #define The comments had to be refined as well as the total size Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix ddr.c] Acked-by: York Sun <yorksun@freescale.com>
41 lines
1.2 KiB
C
41 lines
1.2 KiB
C
/*
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* (C) Copyright 2013 Keymile AG
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* Valentin Longchamp <valentin.longchamp@keymile.com>
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*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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struct law_entry law_table[] = {
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#ifdef CONFIG_SYS_BMAN_MEM_PHYS
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SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
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#endif
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#ifdef CONFIG_SYS_QMAN_MEM_PHYS
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SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
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#endif
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#ifdef CONFIG_SYS_DCSRBAR_PHYS
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/* Limit DCSR to 32M to access NPC Trace Buffer */
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SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
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#endif
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#ifdef CONFIG_SYS_NAND_BASE_PHYS
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
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#endif
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SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
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#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
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SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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#endif
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#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
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SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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