York Sun e1fd16b6f5 mpc85xx: Enable unique mode registers and dynamic ODT for DDR3 ... Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2011-01-19 22:58:23 -06:00
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ddr	mpc85xx: Enable unique mode registers and dynamic ODT for DDR3	2011-01-19 22:58:23 -06:00
cpu.c	powerpc/p2040: Add various p2040 specific information	2011-01-19 22:58:23 -06:00
fdt.c	powerpc/8xxx: Refactor SRIO initialization into common code	2011-01-14 01:32:21 -06:00
fsl_lbc.c	powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)	2011-01-14 01:32:22 -06:00
Makefile	powerpc/8xxx: Refactor SRIO initialization into common code	2011-01-14 01:32:21 -06:00
srio.c	powerpc/8xxx: Refactor SRIO initialization into common code	2011-01-14 01:32:21 -06:00