mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
0b38fffbe4
It could happen (1 out of 100 times) that NAND did not start up correctly after warm rebooting, so we end up with various failures or DMA timed out due to a stalled BCH. When resetting BCH together with GPMI, the issue could not be observed anymore (after 10000+ reboots). We probably need the consistent state already before sending commands to NAND. This behaviour was observed in barebox and kernel, so I assume it affects U-Boot as well. I chose to keep the extra reset for BCH when changing the flash layout to be on the safe side. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> |
||
|---|---|---|
| .. | ||
| nand | ||
| onenand | ||
| spi | ||
| ubi | ||
| at45.c | ||
| cfi_flash.c | ||
| cfi_mtd.c | ||
| dataflash.c | ||
| ftsmc020.c | ||
| jedec_flash.c | ||
| Makefile | ||
| mtdconcat.c | ||
| mtdcore.c | ||
| mtdpart.c | ||
| mw_eeprom.c | ||
| st_smi.c | ||