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https://github.com/brain-hackers/u-boot-brain
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a55957b9ad
The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Move them to per-SoC .c file. Also, fix some PLL comments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
59 lines
2.0 KiB
C
59 lines
2.0 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/delay.h>
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#include "../init.h"
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#include "../sc64-regs.h"
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#include "pll.h"
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/* PLL type: SSC */
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#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
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#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
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#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
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#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */
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#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */
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#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
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#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
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#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
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#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
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/* PLL type: VPLL27 */
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#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
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#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
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/* PLL type: DSPLL */
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#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
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#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
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void uniphier_ld20_pll_init(void)
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{
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uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
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/* do nothing for SPLL */
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uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
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uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
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uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
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uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
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mdelay(1);
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uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
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uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL);
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uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
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uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
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uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
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uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
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uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
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uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
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uniphier_ld20_dspll_init(SC_A2PLLCTRL);
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}
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