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![Graeme Russ](/assets/img/avatar_default.png)
Moved sub-features of the SC520 code which is currently selectively compiled using #ifdef out of sc520.c into individual files selectively compiled via the makefile Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
240 lines
5.9 KiB
C
240 lines
5.9 KiB
C
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* stuff specific for the sc520,
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* but idependent of implementation */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/ic/sc520.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* utility functions for boards based on the AMD sc520
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*
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* void write_mmcr_byte(u16 mmcr, u8 data)
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* void write_mmcr_word(u16 mmcr, u16 data)
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* void write_mmcr_long(u16 mmcr, u32 data)
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*
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* u8 read_mmcr_byte(u16 mmcr)
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* u16 read_mmcr_word(u16 mmcr)
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* u32 read_mmcr_long(u16 mmcr)
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*
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* void init_sc520(void)
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* unsigned long init_sc520_dram(void)
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*/
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static u32 mmcr_base= 0xfffef000;
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void write_mmcr_byte(u16 mmcr, u8 data)
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{
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writeb(data, mmcr+mmcr_base);
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}
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void write_mmcr_word(u16 mmcr, u16 data)
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{
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writew(data, mmcr+mmcr_base);
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}
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void write_mmcr_long(u16 mmcr, u32 data)
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{
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writel(data, mmcr+mmcr_base);
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}
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u8 read_mmcr_byte(u16 mmcr)
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{
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return readb(mmcr+mmcr_base);
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}
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u16 read_mmcr_word(u16 mmcr)
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{
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return readw(mmcr+mmcr_base);
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}
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u32 read_mmcr_long(u16 mmcr)
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{
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return readl(mmcr+mmcr_base);
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}
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void init_sc520(void)
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{
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/* Set the UARTxCTL register at it's slower,
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* baud clock giving us a 1.8432 MHz reference
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*/
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write_mmcr_byte(SC520_UART1CTL, 7);
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write_mmcr_byte(SC520_UART2CTL, 7);
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/* first set the timer pin mapping */
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write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */
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/* enable PCI bus arbitrer */
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write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */
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write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
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write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
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if (CONFIG_SYS_SC520_HIGH_SPEED) {
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write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */
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gd->cpu_clk = 133000000;
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printf("## CPU Speed set to 133MHz\n");
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} else {
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write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */
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printf("## CPU Speed set to 100MHz\n");
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gd->cpu_clk = 100000000;
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}
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/* wait at least one millisecond */
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asm("movl $0x2000,%%ecx\n"
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"wait_loop: pushl %%ecx\n"
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"popl %%ecx\n"
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"loop wait_loop\n": : : "ecx");
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/* turn on the SDRAM write buffer */
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write_mmcr_byte(SC520_DBCTL, 0x11);
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/* turn on the cache and disable write through */
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asm("movl %%cr0, %%eax\n"
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"andl $0x9fffffff, %%eax\n"
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"movl %%eax, %%cr0\n" : : : "eax");
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}
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unsigned long init_sc520_dram(void)
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{
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bd_t *bd = gd->bd;
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u32 dram_present=0;
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u32 dram_ctrl;
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#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
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/* these memory control registers are set up in the assember part,
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* in sc520_asm.S, during 'mem_init'. If we muck with them here,
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* after we are running a stack in RAM, we have troubles. Besides,
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* these refresh and delay values are better ? simply specified
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* outright in the include/configs/{cfg} file since the HW designer
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* simply dictates it.
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*/
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#else
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int val;
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int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
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int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
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int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
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/* set SDRAM speed here */
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refresh_rate/=78;
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if (refresh_rate<=1) {
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val = 0; /* 7.8us */
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} else if (refresh_rate==2) {
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val = 1; /* 15.6us */
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} else if (refresh_rate==3 || refresh_rate==4) {
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val = 2; /* 31.2us */
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} else {
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val = 3; /* 62.4us */
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}
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write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
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val = read_mmcr_byte(SC520_DRCTMCTL);
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val &= 0xf0;
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if (cas_precharge_delay==3) {
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val |= 0x04; /* 3T */
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} else if (cas_precharge_delay==4) {
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val |= 0x08; /* 4T */
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} else if (cas_precharge_delay>4) {
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val |= 0x0c;
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}
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if (ras_cas_delay > 3) {
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val |= 2;
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} else {
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val |= 1;
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}
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write_mmcr_byte(SC520_DRCTMCTL, val);
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#endif
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/* We read-back the configuration of the dram
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* controller that the assembly code wrote */
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dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
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bd->bi_dram[0].start = 0;
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if (dram_ctrl & 0x80) {
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/* bank 0 enabled */
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dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
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bd->bi_dram[0].size = bd->bi_dram[1].start;
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} else {
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bd->bi_dram[0].size = 0;
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bd->bi_dram[1].start = bd->bi_dram[0].start;
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}
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if (dram_ctrl & 0x8000) {
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/* bank 1 enabled */
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dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
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bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
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} else {
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bd->bi_dram[1].size = 0;
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bd->bi_dram[2].start = bd->bi_dram[1].start;
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}
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if (dram_ctrl & 0x800000) {
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/* bank 2 enabled */
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dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
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bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
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} else {
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bd->bi_dram[2].size = 0;
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bd->bi_dram[3].start = bd->bi_dram[2].start;
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}
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if (dram_ctrl & 0x80000000) {
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/* bank 3 enabled */
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dram_present = (dram_ctrl & 0x7f000000) >> 2;
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bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
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} else {
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bd->bi_dram[3].size = 0;
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}
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#if 0
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printf("Configured %d bytes of dram\n", dram_present);
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#endif
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gd->ram_size = dram_present;
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return dram_present;
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}
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#ifdef CONFIG_SYS_SC520_RESET
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void reset_cpu(ulong addr)
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{
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printf("Resetting using SC520 MMCR\n");
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/* Write a '1' to the SYS_RST of the RESCFG MMCR */
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write_mmcr_word(SC520_RESCFG, 0x0001);
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/* NOTREACHED */
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}
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#endif
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