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https://github.com/brain-hackers/u-boot-brain
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3808190af0
In LS2080, SFP has version 3.4. It is in little endian. The base address is 0x01e80200. SFP is used in Secure Boot to read fuses. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
87 lines
2.2 KiB
C
87 lines
2.2 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _FSL_SFP_SNVS_
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#define _FSL_SFP_SNVS_
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#ifdef CONFIG_SYS_FSL_SRK_LE
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#define srk_in32(a) in_le32(a)
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#else
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#define srk_in32(a) in_be32(a)
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#endif
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#ifdef CONFIG_SYS_FSL_SFP_LE
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#define sfp_in32(a) in_le32(a)
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#define sfp_out32(a, v) out_le32(a, v)
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#define sfp_in16(a) in_le16(a)
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#elif defined(CONFIG_SYS_FSL_SFP_BE)
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#define sfp_in32(a) in_be32(a)
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#define sfp_out32(a, v) out_be32(a, v)
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#define sfp_in16(a) in_be16(a)
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#else
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#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined
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#endif
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/* Number of SRKH registers */
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#define NUM_SRKH_REGS 8
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#if defined(CONFIG_SYS_FSL_SFP_VER_3_2) || \
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defined(CONFIG_SYS_FSL_SFP_VER_3_4)
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struct ccsr_sfp_regs {
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u32 ospr; /* 0x200 */
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u32 ospr1; /* 0x204 */
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u32 reserved1[4];
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u32 fswpr; /* 0x218 FSL Section Write Protect */
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u32 fsl_uid; /* 0x21c FSL UID 0 */
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u32 fsl_uid_1; /* 0x220 FSL UID 0 */
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u32 reserved2[12];
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u32 srk_hash[8]; /* 0x254 Super Root Key Hash */
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u32 oem_uid; /* 0x274 OEM UID 0*/
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u32 oem_uid_1; /* 0x278 OEM UID 1*/
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u32 oem_uid_2; /* 0x27c OEM UID 2*/
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u32 oem_uid_3; /* 0x280 OEM UID 3*/
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u32 oem_uid_4; /* 0x284 OEM UID 4*/
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u32 reserved3[8];
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};
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#elif defined(CONFIG_SYS_FSL_SFP_VER_3_0)
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struct ccsr_sfp_regs {
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u32 ospr; /* 0x200 */
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u32 reserved0[14];
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u32 srk_hash[NUM_SRKH_REGS]; /* 0x23c Super Root Key Hash */
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u32 oem_uid; /* 0x9c OEM Unique ID */
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u8 reserved2[0x04];
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u32 ovpr; /* 0xA4 Intent To Secure */
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u8 reserved4[0x08];
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u32 fsl_uid; /* 0xB0 FSL Unique ID */
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u8 reserved5[0x04];
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u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
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u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
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};
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#else
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struct ccsr_sfp_regs {
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u8 reserved0[0x40];
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u32 ospr; /* 0x40 OEM Security Policy Register */
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u8 reserved2[0x38];
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u32 srk_hash[8]; /* 0x7c Super Root Key Hash */
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u32 oem_uid; /* 0x9c OEM Unique ID */
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u8 reserved4[0x4];
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u32 ovpr; /* 0xA4 OEM Validation Policy Register */
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u8 reserved8[0x8];
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u32 fsl_uid; /* 0xB0 FSL Unique ID */
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};
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#endif
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#define ITS_MASK 0x00000004
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#define ITS_BIT 2
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#define OSPR_KEY_REVOC_SHIFT 13
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#define OSPR_KEY_REVOC_MASK 0x0000e000
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#endif
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