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![Ian Campbell](/assets/img/avatar_default.png)
This patch adds DRAM initialisation support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
594 lines
16 KiB
C
594 lines
16 KiB
C
/*
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* sunxi DRAM controller initialization
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* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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*
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* Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
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* and earlier U-Boot Allwiner A10 SPL work
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*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Berg Xing <bergxing@allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Unfortunately the only documentation we have on the sun7i DRAM
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* controller is Allwinner boot0 + boot1 code, and that code uses
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* magic numbers & shifts with no explanations. Hence this code is
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* rather undocumented and full of magic.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/sys_proto.h>
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#define CPU_CFG_CHIP_VER(n) ((n) << 6)
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#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
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#define CPU_CFG_CHIP_REV_A 0x0
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#define CPU_CFG_CHIP_REV_C1 0x1
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#define CPU_CFG_CHIP_REV_C2 0x2
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#define CPU_CFG_CHIP_REV_B 0x3
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/*
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* Wait up to 1s for mask to be clear in given reg.
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*/
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static void await_completion(u32 *reg, u32 mask)
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{
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unsigned long tmo = timer_get_us() + 1000000;
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while (readl(reg) & mask) {
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if (timer_get_us() > tmo)
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panic("Timeout initialising DRAM\n");
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}
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}
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static void mctl_ddr3_reset(void)
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{
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struct sunxi_dram_reg *dram =
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(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
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clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
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udelay(2);
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setbits_le32(&dram->mcr, DRAM_MCR_RESET);
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}
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static void mctl_set_drive(void)
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{
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struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
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clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
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DRAM_MCR_MODE_EN(0x3) |
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0xffc);
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}
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static void mctl_itm_disable(void)
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{
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struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
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clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
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}
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static void mctl_itm_enable(void)
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{
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struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
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clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
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}
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static void mctl_enable_dll0(u32 phase)
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{
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struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
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clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
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((phase >> 16) & 0x3f) << 6);
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clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
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udelay(2);
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clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
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udelay(22);
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clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
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udelay(22);
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}
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/*
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* Note: This differs from pm/standby in that it checks the bus width
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*/
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static void mctl_enable_dllx(u32 phase)
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{
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struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
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u32 i, n, bus_width;
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bus_width = readl(&dram->dcr);
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if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) ==
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DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
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n = DRAM_DCR_NR_DLLCR_32BIT;
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else
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n = DRAM_DCR_NR_DLLCR_16BIT;
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for (i = 1; i < n; i++) {
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clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
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(phase & 0xf) << 14);
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clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
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DRAM_DLLCR_DISABLE);
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phase >>= 4;
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}
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udelay(2);
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for (i = 1; i < n; i++)
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clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
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DRAM_DLLCR_DISABLE);
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udelay(22);
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for (i = 1; i < n; i++)
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clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
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DRAM_DLLCR_NRESET);
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udelay(22);
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}
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static u32 hpcr_value[32] = {
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#ifdef CONFIG_SUN7I
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0x0301, 0x0301, 0x0301, 0x0301,
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0x0301, 0x0301, 0x0301, 0x0301,
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0, 0, 0, 0,
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0, 0, 0, 0,
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0x1031, 0x1031, 0x0735, 0x1035,
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0x1035, 0x0731, 0x1031, 0x0735,
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0x1035, 0x1031, 0x0731, 0x1035,
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0x0001, 0x1031, 0, 0x1031
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/* last row differs from boot0 source table
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* 0x1031, 0x0301, 0x0301, 0x0731
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* but boot0 code skips #28 and #30, and sets #29 and #31 to the
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* value from #28 entry (0x1031)
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*/
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#endif
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};
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static void mctl_configure_hostport(void)
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{
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struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
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u32 i;
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for (i = 0; i < 32; i++)
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writel(hpcr_value[i], &dram->hpcr[i]);
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}
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static void mctl_setup_dram_clock(u32 clk)
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{
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u32 reg_val;
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* setup DRAM PLL */
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reg_val = readl(&ccm->pll5_cfg);
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reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */
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reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */
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reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
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reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
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if (clk >= 540 && clk < 552) {
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/* dram = 540MHz, pll5p = 540MHz */
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reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
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reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
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reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
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reg_val |= CCM_PLL5_CTRL_P(1);
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} else if (clk >= 512 && clk < 528) {
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/* dram = 512MHz, pll5p = 384MHz */
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reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
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reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
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reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
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reg_val |= CCM_PLL5_CTRL_P(2);
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} else if (clk >= 496 && clk < 504) {
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/* dram = 496MHz, pll5p = 372MHz */
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reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
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reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
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reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
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reg_val |= CCM_PLL5_CTRL_P(2);
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} else if (clk >= 468 && clk < 480) {
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/* dram = 468MHz, pll5p = 468MHz */
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reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
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reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
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reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
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reg_val |= CCM_PLL5_CTRL_P(1);
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} else if (clk >= 396 && clk < 408) {
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/* dram = 396MHz, pll5p = 396MHz */
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reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
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reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
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reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
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reg_val |= CCM_PLL5_CTRL_P(1);
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} else {
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/* any other frequency that is a multiple of 24 */
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reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
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reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
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reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
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reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
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}
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reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */
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reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */
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writel(reg_val, &ccm->pll5_cfg);
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udelay(5500);
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setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
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#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
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/* reset GPS */
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clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
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setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
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udelay(1);
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clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
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#endif
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/* setup MBUS clock */
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reg_val = CCM_MBUS_CTRL_GATE |
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CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
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CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
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CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
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writel(reg_val, &ccm->mbus_clk_cfg);
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/*
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* open DRAMC AHB & DLL register clock
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* close it first
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*/
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clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
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udelay(22);
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/* then open it */
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setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
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udelay(22);
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}
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static int dramc_scan_readpipe(void)
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{
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struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
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u32 reg_val;
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/* data training trigger */
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#ifdef CONFIG_SUN7I
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clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
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#endif
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setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
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/* check whether data training process has completed */
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await_completion(&dram->ccr, DRAM_CCR_DATA_TRAINING);
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/* check data training result */
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reg_val = readl(&dram->csr);
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if (reg_val & DRAM_CSR_FAILED)
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return -1;
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return 0;
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}
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static int dramc_scan_dll_para(void)
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{
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struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
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const u32 dqs_dly[7] = {0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc};
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const u32 clk_dly[15] = {0x07, 0x06, 0x05, 0x04, 0x03,
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0x02, 0x01, 0x00, 0x08, 0x10,
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0x18, 0x20, 0x28, 0x30, 0x38};
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u32 clk_dqs_count[15];
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u32 dqs_i, clk_i, cr_i;
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u32 max_val, min_val;
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u32 dqs_index, clk_index;
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/* Find DQS_DLY Pass Count for every CLK_DLY */
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for (clk_i = 0; clk_i < 15; clk_i++) {
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clk_dqs_count[clk_i] = 0;
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clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
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(clk_dly[clk_i] & 0x3f) << 6);
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for (dqs_i = 0; dqs_i < 7; dqs_i++) {
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for (cr_i = 1; cr_i < 5; cr_i++) {
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clrsetbits_le32(&dram->dllcr[cr_i],
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0x4f << 14,
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(dqs_dly[dqs_i] & 0x4f) << 14);
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}
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udelay(2);
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if (dramc_scan_readpipe() == 0)
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clk_dqs_count[clk_i]++;
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}
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}
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/* Test DQS_DLY Pass Count for every CLK_DLY from up to down */
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for (dqs_i = 15; dqs_i > 0; dqs_i--) {
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max_val = 15;
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min_val = 15;
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for (clk_i = 0; clk_i < 15; clk_i++) {
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if (clk_dqs_count[clk_i] == dqs_i) {
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max_val = clk_i;
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if (min_val == 15)
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min_val = clk_i;
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}
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}
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if (max_val < 15)
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break;
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}
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/* Check if Find a CLK_DLY failed */
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if (!dqs_i)
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goto fail;
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/* Find the middle index of CLK_DLY */
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clk_index = (max_val + min_val) >> 1;
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if ((max_val == (15 - 1)) && (min_val > 0))
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/* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle
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* value can be more close to the max_val
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*/
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clk_index = (15 + clk_index) >> 1;
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else if ((max_val < (15 - 1)) && (min_val == 0))
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/* if CLK_DLY[0] is very good, then the middle value can be more
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* close to the min_val
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*/
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clk_index >>= 1;
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if (clk_dqs_count[clk_index] < dqs_i)
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clk_index = min_val;
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/* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan
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* read pipe again
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*/
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clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
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(clk_dly[clk_index] & 0x3f) << 6);
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max_val = 7;
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min_val = 7;
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for (dqs_i = 0; dqs_i < 7; dqs_i++) {
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clk_dqs_count[dqs_i] = 0;
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for (cr_i = 1; cr_i < 5; cr_i++) {
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clrsetbits_le32(&dram->dllcr[cr_i],
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0x4f << 14,
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(dqs_dly[dqs_i] & 0x4f) << 14);
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}
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udelay(2);
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if (dramc_scan_readpipe() == 0) {
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clk_dqs_count[dqs_i] = 1;
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max_val = dqs_i;
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if (min_val == 7)
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min_val = dqs_i;
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}
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}
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if (max_val < 7) {
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dqs_index = (max_val + min_val) >> 1;
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if ((max_val == (7-1)) && (min_val > 0))
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dqs_index = (7 + dqs_index) >> 1;
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else if ((max_val < (7-1)) && (min_val == 0))
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dqs_index >>= 1;
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if (!clk_dqs_count[dqs_index])
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dqs_index = min_val;
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for (cr_i = 1; cr_i < 5; cr_i++) {
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clrsetbits_le32(&dram->dllcr[cr_i],
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0x4f << 14,
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(dqs_dly[dqs_index] & 0x4f) << 14);
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}
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udelay(2);
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return dramc_scan_readpipe();
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}
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fail:
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clrbits_le32(&dram->dllcr[0], 0x3f << 6);
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for (cr_i = 1; cr_i < 5; cr_i++)
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clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14);
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udelay(2);
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return dramc_scan_readpipe();
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}
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static void dramc_clock_output_en(u32 on)
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{
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#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
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struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
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if (on)
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setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
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else
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clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
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#endif
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}
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static const u16 tRFC_table[2][6] = {
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/* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */
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/* DDR2 75ns 105ns 127.5ns 195ns 327.5ns invalid */
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{ 77, 108, 131, 200, 336, 336 },
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/* DDR3 invalid 90ns 110ns 160ns 300ns 350ns */
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{ 93, 93, 113, 164, 308, 359 }
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|
};
|
|
|
|
static void dramc_set_autorefresh_cycle(u32 clk, u32 type, u32 density)
|
|
{
|
|
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
|
|
u32 tRFC, tREFI;
|
|
|
|
tRFC = (tRFC_table[type][density] * clk + 1023) >> 10;
|
|
tREFI = (7987 * clk) >> 10; /* <= 7.8us */
|
|
|
|
writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
|
|
}
|
|
|
|
unsigned long dramc_init(struct dram_para *para)
|
|
{
|
|
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
|
|
u32 reg_val;
|
|
u32 density;
|
|
int ret_val;
|
|
|
|
/* check input dram parameter structure */
|
|
if (!para)
|
|
return 0;
|
|
|
|
/* setup DRAM relative clock */
|
|
mctl_setup_dram_clock(para->clock);
|
|
|
|
/* reset external DRAM */
|
|
mctl_set_drive();
|
|
|
|
/* dram clock off */
|
|
dramc_clock_output_en(0);
|
|
|
|
mctl_itm_disable();
|
|
mctl_enable_dll0(para->tpr3);
|
|
|
|
/* configure external DRAM */
|
|
reg_val = 0x0;
|
|
if (para->type == DRAM_MEMORY_TYPE_DDR3)
|
|
reg_val |= DRAM_DCR_TYPE_DDR3;
|
|
reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
|
|
|
|
if (para->density == 256)
|
|
density = DRAM_DCR_CHIP_DENSITY_256M;
|
|
else if (para->density == 512)
|
|
density = DRAM_DCR_CHIP_DENSITY_512M;
|
|
else if (para->density == 1024)
|
|
density = DRAM_DCR_CHIP_DENSITY_1024M;
|
|
else if (para->density == 2048)
|
|
density = DRAM_DCR_CHIP_DENSITY_2048M;
|
|
else if (para->density == 4096)
|
|
density = DRAM_DCR_CHIP_DENSITY_4096M;
|
|
else if (para->density == 8192)
|
|
density = DRAM_DCR_CHIP_DENSITY_8192M;
|
|
else
|
|
density = DRAM_DCR_CHIP_DENSITY_256M;
|
|
|
|
reg_val |= DRAM_DCR_CHIP_DENSITY(density);
|
|
reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
|
|
reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
|
|
reg_val |= DRAM_DCR_CMD_RANK_ALL;
|
|
reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
|
|
writel(reg_val, &dram->dcr);
|
|
|
|
#ifdef CONFIG_SUN7I
|
|
setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1));
|
|
if (para->tpr4 & 0x2)
|
|
clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1));
|
|
dramc_clock_output_en(1);
|
|
#endif
|
|
|
|
#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
|
|
/* set odt impendance divide ratio */
|
|
reg_val = ((para->zq) >> 8) & 0xfffff;
|
|
reg_val |= ((para->zq) & 0xff) << 20;
|
|
reg_val |= (para->zq) & 0xf0000000;
|
|
writel(reg_val, &dram->zqcr0);
|
|
#endif
|
|
|
|
#ifdef CONFIG_SUN7I
|
|
/* Set CKE Delay to about 1ms */
|
|
setbits_le32(&dram->idcr, 0x1ffff);
|
|
#endif
|
|
|
|
#ifdef CONFIG_SUN7I
|
|
if ((readl(&dram->ppwrsctl) & 0x1) != 0x1)
|
|
mctl_ddr3_reset();
|
|
else
|
|
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
|
|
#endif
|
|
|
|
udelay(1);
|
|
|
|
await_completion(&dram->ccr, DRAM_CCR_INIT);
|
|
|
|
mctl_enable_dllx(para->tpr3);
|
|
|
|
/* set refresh period */
|
|
dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
|
|
|
|
/* set timing parameters */
|
|
writel(para->tpr0, &dram->tpr0);
|
|
writel(para->tpr1, &dram->tpr1);
|
|
writel(para->tpr2, &dram->tpr2);
|
|
|
|
if (para->type == DRAM_MEMORY_TYPE_DDR3) {
|
|
reg_val = DRAM_MR_BURST_LENGTH(0x0);
|
|
#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
|
|
reg_val |= DRAM_MR_POWER_DOWN;
|
|
#endif
|
|
reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
|
|
reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
|
|
} else if (para->type == DRAM_MEMORY_TYPE_DDR2) {
|
|
reg_val = DRAM_MR_BURST_LENGTH(0x2);
|
|
reg_val |= DRAM_MR_CAS_LAT(para->cas);
|
|
reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
|
|
}
|
|
writel(reg_val, &dram->mr);
|
|
|
|
writel(para->emr1, &dram->emr);
|
|
writel(para->emr2, &dram->emr2);
|
|
writel(para->emr3, &dram->emr3);
|
|
|
|
/* set DQS window mode */
|
|
clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
|
|
|
|
#ifdef CONFIG_SUN7I
|
|
/* Command rate timing mode 2T & 1T */
|
|
if (para->tpr4 & 0x1)
|
|
setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
|
|
#endif
|
|
/* reset external DRAM */
|
|
setbits_le32(&dram->ccr, DRAM_CCR_INIT);
|
|
await_completion(&dram->ccr, DRAM_CCR_INIT);
|
|
|
|
#ifdef CONFIG_SUN7I
|
|
/* setup zq calibration manual */
|
|
reg_val = readl(&dram->ppwrsctl);
|
|
if ((reg_val & 0x1) == 1) {
|
|
/* super_standby_flag = 1 */
|
|
|
|
reg_val = readl(0x01c20c00 + 0x120); /* rtc */
|
|
reg_val &= 0x000fffff;
|
|
reg_val |= 0x17b00000;
|
|
writel(reg_val, &dram->zqcr0);
|
|
|
|
/* exit self-refresh state */
|
|
clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
|
|
/* check whether command has been executed */
|
|
await_completion(&dram->dcr, 0x1 << 31);
|
|
|
|
udelay(2);
|
|
|
|
/* dram pad hold off */
|
|
setbits_le32(&dram->ppwrsctl, 0x16510000);
|
|
|
|
await_completion(&dram->ppwrsctl, 0x1);
|
|
|
|
/* exit self-refresh state */
|
|
clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
|
|
|
|
/* check whether command has been executed */
|
|
await_completion(&dram->dcr, 0x1 << 31);
|
|
|
|
udelay(2);
|
|
|
|
/* issue a refresh command */
|
|
clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x13 << 27);
|
|
await_completion(&dram->dcr, 0x1 << 31);
|
|
|
|
udelay(2);
|
|
}
|
|
#endif
|
|
|
|
/* scan read pipe value */
|
|
mctl_itm_enable();
|
|
if (para->tpr3 & (0x1 << 31)) {
|
|
ret_val = dramc_scan_dll_para();
|
|
if (ret_val == 0)
|
|
para->tpr3 =
|
|
(((readl(&dram->dllcr[0]) >> 6) & 0x3f) << 16) |
|
|
(((readl(&dram->dllcr[1]) >> 14) & 0xf) << 0) |
|
|
(((readl(&dram->dllcr[2]) >> 14) & 0xf) << 4) |
|
|
(((readl(&dram->dllcr[3]) >> 14) & 0xf) << 8) |
|
|
(((readl(&dram->dllcr[4]) >> 14) & 0xf) << 12
|
|
);
|
|
} else {
|
|
ret_val = dramc_scan_readpipe();
|
|
}
|
|
|
|
if (ret_val < 0)
|
|
return 0;
|
|
|
|
/* configure all host port */
|
|
mctl_configure_hostport();
|
|
|
|
return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
|
|
}
|