mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
49e93875a6
This is required in the case where U-Boot is typically loaded and run at a particular address, but for some reason the RAM at that location is not available, e.g. due to memory fragmentation loading other boot binaries or firmware, splitting an SMP complex between various different OSs without using e.g. the EL2 second-stage page tables to hide the memory asignments, or due to known ECC failures. Signed-off-by: Stephen Warren <swarren@nvidia.com>
92 lines
2.5 KiB
ArmAsm
92 lines
2.5 KiB
ArmAsm
/*
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* relocate - common relocation function for AArch64 U-Boot
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*
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* (C) Copyright 2013
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* Albert ARIBAUD <albert.u.boot@aribaud.net>
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <elf.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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/*
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* void relocate_code (addr_moni)
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*
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* This function relocates the monitor code.
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* x0 holds the destination address.
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*/
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ENTRY(relocate_code)
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stp x29, x30, [sp, #-32]! /* create a stack frame */
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mov x29, sp
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str x0, [sp, #16]
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/*
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* Copy u-boot from flash to RAM
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*/
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adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */
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subs x9, x0, x1 /* x8 <- Run to copy offset */
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b.eq relocate_done /* skip relocation */
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/*
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* Don't ldr x1, __image_copy_start here, since if the code is already
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* running at an address other than it was linked to, that instruction
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* will load the relocated value of __image_copy_start. To
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* correctly apply relocations, we need to know the linked value.
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*
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* Linked &__image_copy_start, which we know was at
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* CONFIG_SYS_TEXT_BASE, which is stored in _TEXT_BASE, as a non-
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* relocated value, since it isn't a symbol reference.
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*/
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ldr x1, _TEXT_BASE /* x1 <- Linked &__image_copy_start */
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subs x9, x0, x1 /* x9 <- Link to copy offset */
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adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */
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adr x2, __image_copy_end /* x2 <- Run &__image_copy_end */
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copy_loop:
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ldp x10, x11, [x1], #16 /* copy from source address [x1] */
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stp x10, x11, [x0], #16 /* copy to target address [x0] */
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cmp x1, x2 /* until source end address [x2] */
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b.lo copy_loop
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str x0, [sp, #24]
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/*
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* Fix .rela.dyn relocations
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*/
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adr x2, __rel_dyn_start /* x2 <- Run &__rel_dyn_start */
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adr x3, __rel_dyn_end /* x3 <- Run &__rel_dyn_end */
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fixloop:
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ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
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ldr x4, [x2], #8 /* x4 <- addend */
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and x1, x1, #0xffffffff
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cmp x1, #R_AARCH64_RELATIVE
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bne fixnext
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/* relative fix: store addend plus offset at dest location */
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add x0, x0, x9
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add x4, x4, x9
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str x4, [x0]
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fixnext:
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cmp x2, x3
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b.lo fixloop
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relocate_done:
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switch_el x1, 3f, 2f, 1f
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bl hang
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3: mrs x0, sctlr_el3
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b 0f
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2: mrs x0, sctlr_el2
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b 0f
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1: mrs x0, sctlr_el1
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0: tbz w0, #2, 5f /* skip flushing cache if disabled */
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tbz w0, #12, 4f /* skip invalidating i-cache if disabled */
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ic iallu /* i-cache invalidate all */
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isb sy
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4: ldp x0, x1, [sp, #16]
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bl __asm_flush_dcache_range
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5: ldp x29, x30, [sp],#32
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ret
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ENDPROC(relocate_code)
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