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https://github.com/brain-hackers/u-boot-brain
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b113c9b570
This patch adds a simple clock driver for the Marvell Octeon MIPS SoC family. Its for IO clock rate passing via DT in some of the Octeon driver, like I2C. So that we don't need to use the non-mainline API octeon_get_io_clock(). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Lukasz Majewski <lukma@denx.de>
73 lines
1.3 KiB
C
73 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Stefan Roese <sr@denx.de>
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dt-bindings/clock/octeon-clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct octeon_clk_priv {
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u64 core_clk;
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u64 io_clk;
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};
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static int octeon_clk_enable(struct clk *clk)
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{
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/* Nothing to do on Octeon */
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return 0;
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}
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static ulong octeon_clk_get_rate(struct clk *clk)
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{
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struct octeon_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case OCTEON_CLK_CORE:
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return priv->core_clk;
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case OCTEON_CLK_IO:
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return priv->io_clk;
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default:
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return 0;
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}
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return 0;
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}
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static struct clk_ops octeon_clk_ops = {
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.enable = octeon_clk_enable,
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.get_rate = octeon_clk_get_rate,
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};
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static const struct udevice_id octeon_clk_ids[] = {
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{ .compatible = "mrvl,octeon-clk" },
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{ /* sentinel */ }
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};
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static int octeon_clk_probe(struct udevice *dev)
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{
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struct octeon_clk_priv *priv = dev_get_priv(dev);
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/*
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* The clock values are already read into GD, lets just store them
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* in priv data
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*/
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priv->core_clk = gd->cpu_clk;
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priv->io_clk = gd->bus_clk;
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return 0;
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}
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U_BOOT_DRIVER(clk_octeon) = {
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.name = "clk_octeon",
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.id = UCLASS_CLK,
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.of_match = octeon_clk_ids,
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.ops = &octeon_clk_ops,
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.probe = octeon_clk_probe,
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.priv_auto_alloc_size = sizeof(struct octeon_clk_priv),
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};
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