mirror of
https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
361 lines
8.3 KiB
C
361 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2015 Sanchayan Maity <sanchayan.maity@toradex.com>
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* Copyright (C) 2015 Toradex AG
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*
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* Based on ehci-mx6 driver
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*/
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#include <common.h>
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#include <dm.h>
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#include <usb.h>
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#include <errno.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/regs-usbphy.h>
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#include <usb/ehci-ci.h>
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#include <linux/libfdt.h>
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#include <fdtdec.h>
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#include "ehci.h"
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#define USB_NC_REG_OFFSET 0x00000800
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#define ANADIG_PLL_CTRL_EN_USB_CLKS (1 << 6)
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#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
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#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
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/* USBCMD */
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#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
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#define UCMD_RESET (1 << 1) /* controller reset */
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DECLARE_GLOBAL_DATA_PTR;
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static const unsigned phy_bases[] = {
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USB_PHY0_BASE_ADDR,
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USB_PHY1_BASE_ADDR,
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};
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static const unsigned nc_reg_bases[] = {
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USBC0_BASE_ADDR,
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USBC1_BASE_ADDR,
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};
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static void usb_internal_phy_clock_gate(int index)
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{
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void __iomem *phy_reg;
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phy_reg = (void __iomem *)phy_bases[index];
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clrbits_le32(phy_reg + USBPHY_CTRL, USBPHY_CTRL_CLKGATE);
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}
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static void usb_power_config(int index)
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{
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struct anadig_reg __iomem *anadig =
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(struct anadig_reg __iomem *)ANADIG_BASE_ADDR;
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void __iomem *pll_ctrl;
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switch (index) {
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case 0:
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pll_ctrl = &anadig->pll3_ctrl;
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clrbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_BYPASS);
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setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE
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| ANADIG_PLL3_CTRL_POWERDOWN
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| ANADIG_PLL_CTRL_EN_USB_CLKS);
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break;
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case 1:
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pll_ctrl = &anadig->pll7_ctrl;
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clrbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_BYPASS);
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setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE
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| ANADIG_PLL7_CTRL_POWERDOWN
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| ANADIG_PLL_CTRL_EN_USB_CLKS);
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break;
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default:
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return;
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}
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}
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static void usb_phy_enable(int index, struct usb_ehci *ehci)
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{
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void __iomem *phy_reg;
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void __iomem *phy_ctrl;
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void __iomem *usb_cmd;
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phy_reg = (void __iomem *)phy_bases[index];
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phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
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usb_cmd = (void __iomem *)&ehci->usbcmd;
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/* Stop then Reset */
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clrbits_le32(usb_cmd, UCMD_RUN_STOP);
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while (readl(usb_cmd) & UCMD_RUN_STOP)
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;
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setbits_le32(usb_cmd, UCMD_RESET);
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while (readl(usb_cmd) & UCMD_RESET)
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;
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/* Reset USBPHY module */
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setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
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udelay(10);
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/* Remove CLKGATE and SFTRST */
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clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
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udelay(10);
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/* Power up the PHY */
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writel(0, phy_reg + USBPHY_PWD);
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/* Enable FS/LS device */
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setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
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USBPHY_CTRL_ENUTMILEVEL3);
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}
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static void usb_oc_config(int index)
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{
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void __iomem *ctrl;
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ctrl = (void __iomem *)(nc_reg_bases[index] + USB_NC_REG_OFFSET);
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setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
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setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
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}
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int __weak board_usb_phy_mode(int port)
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{
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return 0;
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}
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int __weak board_ehci_hcd_init(int port)
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{
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return 0;
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}
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int ehci_vf_common_init(struct usb_ehci *ehci, int index)
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{
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int ret;
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/* Do board specific initialisation */
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ret = board_ehci_hcd_init(index);
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if (ret)
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return ret;
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usb_power_config(index);
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usb_oc_config(index);
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usb_internal_phy_clock_gate(index);
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usb_phy_enable(index, ehci);
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return 0;
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}
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#ifndef CONFIG_DM_USB
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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struct usb_ehci *ehci;
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enum usb_init_type type;
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int ret;
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if (index >= ARRAY_SIZE(nc_reg_bases))
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return -EINVAL;
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ehci = (struct usb_ehci *)nc_reg_bases[index];
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ret = ehci_vf_common_init(index);
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if (ret)
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return ret;
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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type = board_usb_phy_mode(index);
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if (type != init)
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return -ENODEV;
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if (init == USB_INIT_DEVICE) {
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setbits_le32(&ehci->usbmode, CM_DEVICE);
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writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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} else if (init == USB_INIT_HOST) {
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setbits_le32(&ehci->usbmode, CM_HOST);
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writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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}
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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#else
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/* Possible port types (dual role mode) */
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enum dr_mode {
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DR_MODE_NONE = 0,
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DR_MODE_HOST, /* supports host operation */
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DR_MODE_DEVICE, /* supports device operation */
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DR_MODE_OTG, /* supports both */
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};
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struct ehci_vf_priv_data {
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struct ehci_ctrl ctrl;
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struct usb_ehci *ehci;
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struct gpio_desc cdet_gpio;
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enum usb_init_type init_type;
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enum dr_mode dr_mode;
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u32 portnr;
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};
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static int vf_usb_ofdata_to_platdata(struct udevice *dev)
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{
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struct ehci_vf_priv_data *priv = dev_get_priv(dev);
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const void *dt_blob = gd->fdt_blob;
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int node = dev_of_offset(dev);
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const char *mode;
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priv->portnr = dev->seq;
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priv->ehci = (struct usb_ehci *)devfdt_get_addr(dev);
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mode = fdt_getprop(dt_blob, node, "dr_mode", NULL);
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if (mode) {
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if (0 == strcmp(mode, "host")) {
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priv->dr_mode = DR_MODE_HOST;
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priv->init_type = USB_INIT_HOST;
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} else if (0 == strcmp(mode, "peripheral")) {
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priv->dr_mode = DR_MODE_DEVICE;
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priv->init_type = USB_INIT_DEVICE;
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} else if (0 == strcmp(mode, "otg")) {
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priv->dr_mode = DR_MODE_OTG;
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/*
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* We set init_type to device by default when OTG
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* mode is requested. If a valid gpio is provided
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* we will switch the init_type based on the state
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* of the gpio pin.
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*/
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priv->init_type = USB_INIT_DEVICE;
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} else {
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debug("%s: Cannot decode dr_mode '%s'\n",
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__func__, mode);
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return -EINVAL;
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}
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} else {
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priv->dr_mode = DR_MODE_HOST;
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priv->init_type = USB_INIT_HOST;
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}
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if (priv->dr_mode == DR_MODE_OTG) {
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gpio_request_by_name_nodev(offset_to_ofnode(node),
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"fsl,cdet-gpio", 0, &priv->cdet_gpio,
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GPIOD_IS_IN);
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if (dm_gpio_is_valid(&priv->cdet_gpio)) {
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if (dm_gpio_get_value(&priv->cdet_gpio))
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priv->init_type = USB_INIT_DEVICE;
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else
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priv->init_type = USB_INIT_HOST;
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}
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}
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return 0;
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}
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static int vf_init_after_reset(struct ehci_ctrl *dev)
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{
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struct ehci_vf_priv_data *priv = dev->priv;
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enum usb_init_type type = priv->init_type;
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struct usb_ehci *ehci = priv->ehci;
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int ret;
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ret = ehci_vf_common_init(priv->ehci, priv->portnr);
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if (ret)
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return ret;
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if (type == USB_INIT_DEVICE)
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return 0;
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setbits_le32(&ehci->usbmode, CM_HOST);
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writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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mdelay(10);
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return 0;
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}
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static const struct ehci_ops vf_ehci_ops = {
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.init_after_reset = vf_init_after_reset
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};
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static int vf_usb_bind(struct udevice *dev)
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{
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static int num_controllers;
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/*
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* Without this hack, if we return ENODEV for USB Controller 0, on
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* probe for the next controller, USB Controller 1 will be given a
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* sequence number of 0. This conflicts with our requirement of
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* sequence numbers while initialising the peripherals.
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*/
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dev->req_seq = num_controllers;
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num_controllers++;
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return 0;
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}
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static int ehci_usb_probe(struct udevice *dev)
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{
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struct usb_platdata *plat = dev_get_platdata(dev);
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struct ehci_vf_priv_data *priv = dev_get_priv(dev);
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struct usb_ehci *ehci = priv->ehci;
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struct ehci_hccr *hccr;
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struct ehci_hcor *hcor;
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int ret;
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ret = ehci_vf_common_init(ehci, priv->portnr);
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if (ret)
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return ret;
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if (priv->init_type != plat->init_type)
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return -ENODEV;
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if (priv->init_type == USB_INIT_HOST) {
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setbits_le32(&ehci->usbmode, CM_HOST);
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writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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}
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mdelay(10);
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hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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hcor = (struct ehci_hcor *)((uint32_t)hccr +
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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return ehci_register(dev, hccr, hcor, &vf_ehci_ops, 0, priv->init_type);
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}
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static const struct udevice_id vf_usb_ids[] = {
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{ .compatible = "fsl,vf610-usb" },
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{ }
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};
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U_BOOT_DRIVER(usb_ehci) = {
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.name = "ehci_vf",
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.id = UCLASS_USB,
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.of_match = vf_usb_ids,
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.bind = vf_usb_bind,
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.probe = ehci_usb_probe,
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.remove = ehci_deregister,
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.ops = &ehci_usb_ops,
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.ofdata_to_platdata = vf_usb_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct usb_platdata),
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.priv_auto_alloc_size = sizeof(struct ehci_vf_priv_data),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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#endif
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