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https://github.com/brain-hackers/u-boot-brain
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e8cc3f04b1
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash memory. The current memory map only supports up to 128 MiB Flash. This patch adds the configuration option CONFIG_TQM_BIGFLASH. If set, up to 1 GiB flash is supported. To achieve this, the memory map has to be adjusted in great parts (for example the CCSRBAR is moved from 0xE0000000 to 0xA0000000). If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new memory map also has to be considered in the kernel (changed CCSRBAR address, changed PCI IO base address, ...). Please use an appropriate Flat Device Tree blob (tqm8548.dtb). Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
249 lines
8.0 KiB
C
249 lines
8.0 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024,
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CFG_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024,
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CFG_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024,
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CFG_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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#ifndef CONFIG_TQM_BIGFLASH
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/*
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* TLB 0, 1: 128M Non-cacheable, guarded
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* 0xf8000000 128M FLASH
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* Out of reset this entry is only 4K.
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*/
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SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 1, BOOKE_PAGESZ_64M, 1),
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SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000,
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CFG_FLASH_BASE + 0x4000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 0, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 2: 256M Non-cacheable, guarded
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* 0x80000000 256M PCI1 MEM First half
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*/
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SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 3: 256M Non-cacheable, guarded
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* 0x90000000 256M PCI1 MEM Second half
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*/
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SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
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CFG_PCI1_MEM_PHYS + 0x10000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 3, BOOKE_PAGESZ_256M, 1),
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#ifdef CONFIG_PCIE1
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/*
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* TLB 4: 256M Non-cacheable, guarded
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* 0xc0000000 256M PCI express MEM First half
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*/
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SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 4, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 5: 256M Non-cacheable, guarded
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* 0xd0000000 256M PCI express MEM Second half
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*/
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SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000,
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CFG_PCIE1_MEM_BASE + 0x10000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 5, BOOKE_PAGESZ_256M, 1),
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#else /* !CONFIG_PCIE */
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/*
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* TLB 4: 256M Non-cacheable, guarded
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* 0xc0000000 256M Rapid IO MEM First half
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*/
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SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 4, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 5: 256M Non-cacheable, guarded
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* 0xd0000000 256M Rapid IO MEM Second half
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*/
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SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000,
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CFG_RIO_MEM_BASE + 0x10000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 5, BOOKE_PAGESZ_256M, 1),
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#endif /* CONFIG_PCIE */
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/*
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* TLB 6: 64M Non-cacheable, guarded
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* 0xe0000000 1M CCSRBAR
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* 0xe2000000 16M PCI1 IO
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* 0xe3000000 16M CAN and NAND Flash
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*/
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SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 6, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
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* 0x00000000 512M DDR System memory
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* Without SPD EEPROM configured DDR, this must be setup manually.
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* Make sure the TLB count at the top of this table is correct.
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* Likely it needs to be increased by two for these entries.
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*/
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SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 7, BOOKE_PAGESZ_256M, 1),
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SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
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CFG_DDR_SDRAM_BASE + 0x10000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 8, BOOKE_PAGESZ_256M, 1),
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#ifdef CONFIG_PCIE1
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/*
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* TLB 9: 16M Non-cacheable, guarded
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* 0xef000000 16M PCI express IO
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*/
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SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 9, BOOKE_PAGESZ_16M, 1),
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#endif /* CONFIG_PCIE */
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#else /* CONFIG_TQM_BIGFLASH */
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/*
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* TLB 0,1,2,3: 1G Non-cacheable, guarded
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* 0xc0000000 1G FLASH
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* Out of reset this entry is only 4K.
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*/
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SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 3, BOOKE_PAGESZ_256M, 1),
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SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000,
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CFG_FLASH_BASE + 0x10000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000,
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CFG_FLASH_BASE + 0x20000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 1, BOOKE_PAGESZ_256M, 1),
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SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000,
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CFG_FLASH_BASE + 0x30000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 0, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 4: 256M Non-cacheable, guarded
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* 0x80000000 256M PCI1 MEM First half
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*/
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SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 4, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 5: 256M Non-cacheable, guarded
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* 0x90000000 256M PCI1 MEM Second half
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*/
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SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
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CFG_PCI1_MEM_PHYS + 0x10000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 5, BOOKE_PAGESZ_256M, 1),
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#ifdef CONFIG_PCIE1
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/*
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* TLB 6: 256M Non-cacheable, guarded
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* 0xc0000000 256M PCI express MEM First half
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*/
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SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 6, BOOKE_PAGESZ_256M, 1),
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#else /* !CONFIG_PCIE */
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/*
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* TLB 6: 256M Non-cacheable, guarded
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* 0xb0000000 256M Rapid IO MEM First half
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*/
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SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 6, BOOKE_PAGESZ_256M, 1),
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#endif /* CONFIG_PCIE */
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/*
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* TLB 7: 64M Non-cacheable, guarded
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* 0xa0000000 1M CCSRBAR
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* 0xa2000000 16M PCI1 IO
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* 0xa3000000 16M CAN and NAND Flash
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*/
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SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 7, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 8+9: 512M DDR, cache disabled (needed for memory test)
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* 0x00000000 512M DDR System memory
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* Without SPD EEPROM configured DDR, this must be setup manually.
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* Make sure the TLB count at the top of this table is correct.
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* Likely it needs to be increased by two for these entries.
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*/
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SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 8, BOOKE_PAGESZ_256M, 1),
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SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
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CFG_DDR_SDRAM_BASE + 0x10000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 9, BOOKE_PAGESZ_256M, 1),
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#ifdef CONFIG_PCIE1
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/*
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* TLB 10: 16M Non-cacheable, guarded
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* 0xaf000000 16M PCI express IO
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*/
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SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 10, BOOKE_PAGESZ_16M, 1),
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#endif /* CONFIG_PCIE */
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#endif /* CONFIG_TQM_BIGFLASH */
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};
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int num_tlb_entries = ARRAY_SIZE (tlb_table);
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