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![Anatolij Gustschin](/assets/img/avatar_default.png)
The new IPEK01 board can use the 32 bpp mode for the Lime graphics controller. For this mode, video accelaration does not work. This patch makes the accelaration configurable via CONFIG_VIDEO_MB862xx_ACCEL, which is enabled for the lwmon5 and the socrates board for backward compatibility. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
479 lines
12 KiB
C
479 lines
12 KiB
C
/*
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* (C) Copyright 2007
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* DENX Software Engineering, Anatolij Gustschin, agust@denx.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
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* PCI and video mode code was derived from smiLynxEM driver.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <video_fb.h>
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#include "videomodes.h"
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#include <mb862xx.h>
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#if defined(CONFIG_POST)
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#include <post.h>
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#endif
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/*
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* Graphic Device
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*/
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GraphicDevice mb862xx;
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/*
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* 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
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*/
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#define VIDEO_MEM_SIZE 0x01FC0000
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#if defined(CONFIG_PCI)
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#if defined(CONFIG_VIDEO_CORALP)
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static struct pci_device_id supported[] = {
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{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
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{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
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{ }
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};
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/* Internal clock frequency divider table, index is mode number */
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unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
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#endif
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#endif
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#if defined(CONFIG_VIDEO_CORALP)
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#define rd_io in32r
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#define wr_io out32r
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#else
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#define rd_io(addr) in_be32((volatile unsigned *)(addr))
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#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
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#endif
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#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
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#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
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(val))
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#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
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#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
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(val))
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#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
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#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
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#if defined(CONFIG_VIDEO_CORALP)
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#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
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#else
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#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
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#endif
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#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
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(GC_DISP_BASE | GC_L0PAL0) + \
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((idx) << 2)), (val))
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#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
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static void gdc_sw_reset (void)
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{
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GraphicDevice *dev = &mb862xx;
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HOST_WR_REG (GC_SRST, 0x1);
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udelay (500);
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video_hw_init ();
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}
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static void de_wait (void)
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{
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GraphicDevice *dev = &mb862xx;
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int lc = 0x10000;
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/*
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* Sync with software writes to framebuffer,
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* try to reset if engine locked
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*/
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while (DE_RD_REG (GC_CTR) & 0x00000131)
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if (lc-- < 0) {
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gdc_sw_reset ();
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puts ("gdc reset done after drawing engine lock.\n");
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break;
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}
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}
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static void de_wait_slots (int slots)
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{
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GraphicDevice *dev = &mb862xx;
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int lc = 0x10000;
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/* Wait for free fifo slots */
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while (DE_RD_REG (GC_IFCNT) < slots)
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if (lc-- < 0) {
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gdc_sw_reset ();
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puts ("gdc reset done after drawing engine lock.\n");
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break;
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}
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}
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#endif
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#if !defined(CONFIG_VIDEO_CORALP)
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static void board_disp_init (void)
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{
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GraphicDevice *dev = &mb862xx;
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const gdc_regs *regs = board_get_regs ();
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while (regs->index) {
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DISP_WR_REG (regs->index, regs->value);
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regs++;
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}
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}
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#endif
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/*
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* Init drawing engine if accel enabled.
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* Also clears visible framebuffer.
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*/
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static void de_init (void)
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{
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GraphicDevice *dev = &mb862xx;
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#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
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int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
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dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
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/* Setup mode and fbbase, xres, fg, bg */
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de_wait_slots (2);
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DE_WR_FIFO (0xf1010108);
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DE_WR_FIFO (cf | 0x0300);
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DE_WR_REG (GC_FBR, 0x0);
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DE_WR_REG (GC_XRES, dev->winSizeX);
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DE_WR_REG (GC_FC, 0x0);
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DE_WR_REG (GC_BC, 0x0);
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/* Reset clipping */
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DE_WR_REG (GC_CXMIN, 0x0);
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DE_WR_REG (GC_CXMAX, dev->winSizeX);
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DE_WR_REG (GC_CYMIN, 0x0);
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DE_WR_REG (GC_CYMAX, dev->winSizeY);
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/* Clear framebuffer using drawing engine */
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de_wait_slots (3);
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DE_WR_FIFO (0x09410000);
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DE_WR_FIFO (0x00000000);
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DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
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/* sync with SW access to framebuffer */
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de_wait ();
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#else
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unsigned int i, *p;
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i = dev->winSizeX * dev->winSizeY;
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p = (unsigned int *)dev->frameAdrs;
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while (i--)
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*p++ = 0;
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#endif
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}
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#if defined(CONFIG_VIDEO_CORALP)
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unsigned int pci_video_init (void)
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{
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GraphicDevice *dev = &mb862xx;
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pci_dev_t devbusfn;
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if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
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puts ("PCI video controller not found!\n");
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return 0;
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}
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/* PCI setup */
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pci_write_config_dword (devbusfn, PCI_COMMAND,
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(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
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pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
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dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
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if (dev->frameAdrs == 0) {
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puts ("PCI config: failed to get base address\n");
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return 0;
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}
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dev->pciBase = dev->frameAdrs;
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/* Setup clocks and memory mode for Coral-P Eval. Board */
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HOST_WR_REG (GC_CCF, 0x00090000);
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udelay (200);
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HOST_WR_REG (GC_MMR, 0x11d7fa13);
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udelay (100);
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return dev->frameAdrs;
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}
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unsigned int card_init (void)
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{
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GraphicDevice *dev = &mb862xx;
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unsigned int cf, videomode, div = 0;
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unsigned long t1, hsync, vsync;
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char *penv;
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int tmp, i, bpp;
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struct ctfb_res_modes *res_mode;
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struct ctfb_res_modes var_mode;
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memset (dev, 0, sizeof (GraphicDevice));
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if (!pci_video_init ())
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return 0;
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puts ("CoralP\n");
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tmp = 0;
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videomode = 0x310;
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/* get video mode via environment */
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if ((penv = getenv ("videomode")) != NULL) {
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/* decide if it is a string */
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if (penv[0] <= '9') {
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videomode = (int) simple_strtoul (penv, NULL, 16);
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tmp = 1;
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}
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} else {
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tmp = 1;
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}
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if (tmp) {
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/* parameter are vesa modes, search params */
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for (i = 0; i < VESA_MODES_COUNT; i++) {
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if (vesa_modes[i].vesanr == videomode)
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break;
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}
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if (i == VESA_MODES_COUNT) {
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printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
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videomode);
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i = 0;
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}
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res_mode = (struct ctfb_res_modes *)
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&res_mode_init[vesa_modes[i].resindex];
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if (vesa_modes[i].resindex > 2) {
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puts ("\tUnsupported resolution, using default\n");
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bpp = vesa_modes[1].bits_per_pixel;
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div = fr_div[1];
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}
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bpp = vesa_modes[i].bits_per_pixel;
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div = fr_div[vesa_modes[i].resindex];
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} else {
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res_mode = (struct ctfb_res_modes *) &var_mode;
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bpp = video_get_params (res_mode, penv);
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}
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/* calculate hsync and vsync freq (info only) */
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t1 = (res_mode->left_margin + res_mode->xres +
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res_mode->right_margin + res_mode->hsync_len) / 8;
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t1 *= 8;
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t1 *= res_mode->pixclock;
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t1 /= 1000;
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hsync = 1000000000L / t1;
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t1 *= (res_mode->upper_margin + res_mode->yres +
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res_mode->lower_margin + res_mode->vsync_len);
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t1 /= 1000;
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vsync = 1000000000L / t1;
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/* fill in Graphic device struct */
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sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
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res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
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printf ("\t%s\n", dev->modeIdent);
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dev->winSizeX = res_mode->xres;
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dev->winSizeY = res_mode->yres;
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dev->memSize = VIDEO_MEM_SIZE;
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switch (bpp) {
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case 8:
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dev->gdfIndex = GDF__8BIT_INDEX;
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dev->gdfBytesPP = 1;
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break;
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case 15:
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case 16:
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dev->gdfIndex = GDF_15BIT_555RGB;
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dev->gdfBytesPP = 2;
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break;
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default:
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printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
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bpp);
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puts ("\tfallback to 15bpp\n");
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dev->gdfIndex = GDF_15BIT_555RGB;
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dev->gdfBytesPP = 2;
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}
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/* Setup dot clock (internal pll, division rate) */
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DISP_WR_REG (GC_DCM1, div);
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/* L0 init */
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cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
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DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
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(dev->winSizeY - 1) | cf);
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DISP_WR_REG (GC_L0OA0, 0x0);
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DISP_WR_REG (GC_L0DA0, 0x0);
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DISP_WR_REG (GC_L0DY_L0DX, 0x0);
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DISP_WR_REG (GC_L0EM, 0x0);
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DISP_WR_REG (GC_L0WY_L0WX, 0x0);
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DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
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/* Display timing init */
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DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
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res_mode->left_margin +
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res_mode->right_margin +
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res_mode->hsync_len - 1) << 16);
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DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
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(dev->winSizeX - 1));
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DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
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(res_mode->hsync_len - 1) << 16 |
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(dev->winSizeX +
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res_mode->right_margin - 1));
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DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
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res_mode->upper_margin +
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res_mode->vsync_len - 1) << 16);
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DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
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(dev->winSizeY +
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res_mode->lower_margin - 1));
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DISP_WR_REG (GC_WY_WX, 0x0);
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DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
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/* Display enable, L0 layer */
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DISP_WR_REG (GC_DCM1, 0x80010000 | div);
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return dev->frameAdrs;
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}
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#endif
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#if !defined(CONFIG_VIDEO_CORALP)
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int mb862xx_probe(unsigned int addr)
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{
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GraphicDevice *dev = &mb862xx;
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unsigned int reg;
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dev->frameAdrs = addr;
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dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
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/* Try to access GDC ID/Revision registers */
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reg = HOST_RD_REG (GC_CID);
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reg = HOST_RD_REG (GC_CID);
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if (reg == 0x303) {
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reg = DE_RD_REG(GC_REV);
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reg = DE_RD_REG(GC_REV);
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if ((reg & ~0xff) == 0x20050100)
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return MB862XX_TYPE_LIME;
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}
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return 0;
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}
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#endif
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void *video_hw_init (void)
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{
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GraphicDevice *dev = &mb862xx;
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puts ("Video: Fujitsu ");
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memset (dev, 0, sizeof (GraphicDevice));
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#if defined(CONFIG_VIDEO_CORALP)
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if (card_init () == 0)
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return NULL;
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#else
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/*
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* Preliminary init of the onboard graphic controller,
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* retrieve base address
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*/
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if ((dev->frameAdrs = board_video_init ()) == 0) {
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puts ("Controller not found!\n");
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return NULL;
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} else {
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puts ("Lime\n");
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/* Set Change of Clock Frequency Register */
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HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
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/* Delay required */
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udelay(300);
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/* Set Memory I/F Mode Register) */
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HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
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}
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#endif
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de_init ();
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#if !defined(CONFIG_VIDEO_CORALP)
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board_disp_init ();
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#endif
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#if (defined(CONFIG_LWMON5) || \
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defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
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/* Lamp on */
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board_backlight_switch (1);
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#endif
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return dev;
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}
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/*
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* Set a RGB color in the LUT
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*/
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void video_set_lut (unsigned int index, unsigned char r,
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unsigned char g, unsigned char b)
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{
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GraphicDevice *dev = &mb862xx;
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L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
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}
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#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
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/*
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* Drawing engine Fill and BitBlt screen region
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*/
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void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
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unsigned int dst_y, unsigned int dim_x,
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unsigned int dim_y, unsigned int color)
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{
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GraphicDevice *dev = &mb862xx;
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de_wait_slots (3);
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DE_WR_REG (GC_FC, color);
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DE_WR_FIFO (0x09410000);
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DE_WR_FIFO ((dst_y << 16) | dst_x);
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DE_WR_FIFO ((dim_y << 16) | dim_x);
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de_wait ();
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}
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void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
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unsigned int src_y, unsigned int dst_x,
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unsigned int dst_y, unsigned int width,
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unsigned int height)
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{
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GraphicDevice *dev = &mb862xx;
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unsigned int ctrl = 0x0d000000L;
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if (src_x >= dst_x && src_y >= dst_y)
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ctrl |= 0x00440000L;
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else if (src_x >= dst_x && src_y <= dst_y)
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ctrl |= 0x00460000L;
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else if (src_x <= dst_x && src_y >= dst_y)
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ctrl |= 0x00450000L;
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else
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ctrl |= 0x00470000L;
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de_wait_slots (4);
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DE_WR_FIFO (ctrl);
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DE_WR_FIFO ((src_y << 16) | src_x);
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DE_WR_FIFO ((dst_y << 16) | dst_x);
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DE_WR_FIFO ((height << 16) | width);
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de_wait (); /* sync */
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}
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#endif
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