mirror of
https://github.com/brain-hackers/u-boot-brain
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200 lines
4.3 KiB
C
200 lines
4.3 KiB
C
/*
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* Support for indirect PCI bridges.
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*
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* Copyright (c) Freescale Semiconductor, Inc.
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* 2006. All rights reserved.
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*
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* Jason Jin <Jason.jin@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* partly derived from
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* arch/powerpc/platforms/86xx/mpc86xx_pcie.c
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*/
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#include <common.h>
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#ifdef CONFIG_PCI
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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#define PCI_CFG_OUT out_be32
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#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
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static int
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indirect_read_config_pcie(struct pci_controller *hose,
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pci_dev_t dev,
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int offset,
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int len,
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u32 *val)
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{
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int bus = PCI_BUS(dev);
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volatile unsigned char *cfg_data;
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u32 temp;
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PEX_FIX;
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if (bus == 0xff) {
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PCI_CFG_OUT(hose->cfg_addr,
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dev | (offset & 0xfc) | 0x80000001);
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} else {
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PCI_CFG_OUT(hose->cfg_addr,
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dev | (offset & 0xfc) | 0x80000000);
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}
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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/* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
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cfg_data = hose->cfg_data;
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PEX_FIX;
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temp = in_le32((u32 *) cfg_data);
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switch (len) {
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case 1:
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*val = (temp >> (((offset & 3)) * 8)) & 0xff;
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break;
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case 2:
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*val = (temp >> (((offset & 3)) * 8)) & 0xffff;
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break;
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default:
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*val = temp;
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break;
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}
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return 0;
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}
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static int
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indirect_write_config_pcie(struct pci_controller *hose,
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pci_dev_t dev,
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int offset,
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int len,
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u32 val)
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{
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int bus = PCI_BUS(dev);
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volatile unsigned char *cfg_data;
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u32 temp;
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PEX_FIX;
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if (bus == 0xff) {
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PCI_CFG_OUT(hose->cfg_addr,
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dev | (offset & 0xfc) | 0x80000001);
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} else {
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PCI_CFG_OUT(hose->cfg_addr,
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dev | (offset & 0xfc) | 0x80000000);
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}
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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/* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
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cfg_data = hose->cfg_data;
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switch (len) {
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case 1:
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PEX_FIX;
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temp = in_le32((u32 *) cfg_data);
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temp = (temp & ~(0xff << ((offset & 3) * 8))) |
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(val << ((offset & 3) * 8));
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PEX_FIX;
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out_le32((u32 *) cfg_data, temp);
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break;
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case 2:
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PEX_FIX;
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temp = in_le32((u32 *) cfg_data);
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temp = (temp & ~(0xffff << ((offset & 3) * 8)));
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temp |= (val << ((offset & 3) * 8));
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PEX_FIX;
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out_le32((u32 *) cfg_data, temp);
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break;
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default:
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PEX_FIX;
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out_le32((u32 *) cfg_data, val);
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break;
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}
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PEX_FIX;
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return 0;
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}
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static int
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indirect_read_config_byte_pcie(struct pci_controller *hose,
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pci_dev_t dev,
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int offset,
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u8 *val)
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{
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u32 val32;
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indirect_read_config_pcie(hose, dev, offset, 1, &val32);
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*val = (u8) val32;
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return 0;
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}
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static int
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indirect_read_config_word_pcie(struct pci_controller *hose,
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pci_dev_t dev,
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int offset,
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u16 *val)
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{
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u32 val32;
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indirect_read_config_pcie(hose, dev, offset, 2, &val32);
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*val = (u16) val32;
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return 0;
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}
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static int
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indirect_read_config_dword_pcie(struct pci_controller *hose,
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pci_dev_t dev,
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int offset,
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u32 *val)
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{
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return indirect_read_config_pcie(hose, dev, offset, 4, val);
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}
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static int
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indirect_write_config_byte_pcie(struct pci_controller *hose,
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pci_dev_t dev,
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int offset,
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u8 val)
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{
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return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val);
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}
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static int
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indirect_write_config_word_pcie(struct pci_controller *hose,
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pci_dev_t dev,
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int offset,
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unsigned short val)
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{
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return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val);
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}
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static int
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indirect_write_config_dword_pcie(struct pci_controller *hose,
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pci_dev_t dev,
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int offset,
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u32 val)
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{
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return indirect_write_config_pcie(hose, dev, offset, 4, val);
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}
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void
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pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
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{
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pci_set_ops(hose,
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indirect_read_config_byte_pcie,
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indirect_read_config_word_pcie,
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indirect_read_config_dword_pcie,
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indirect_write_config_byte_pcie,
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indirect_write_config_word_pcie,
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indirect_write_config_dword_pcie);
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hose->cfg_addr = (unsigned int *)cfg_addr;
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hose->cfg_data = (unsigned char *)cfg_data;
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}
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#endif /* CONFIG_PCI */
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