mirror of
https://github.com/brain-hackers/u-boot-brain
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192 lines
5.8 KiB
C
192 lines
5.8 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright (C) 2003 Motorola Inc.
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* Xianghua Xiao (x.xiao@motorola.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* PCI Configuration space access support for MPC8220 PCI Bridge
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*/
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#include <common.h>
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#include <mpc8220.h>
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#include <pci.h>
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#include <asm/io.h>
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#if defined(CONFIG_PCI)
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/* System RAM mapped over PCI */
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#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
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#define cfg_read(val, addr, type, op) *val = op((type)(addr));
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#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
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#define PCI_OP(rw, size, type, op, mask) \
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int mpc8220_pci_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, type val) \
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{ \
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u32 addr = 0; \
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u16 cfg_type = 0; \
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addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
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out_be32(hose->cfg_addr, addr); \
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__asm__ __volatile__("sync"); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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out_be32(hose->cfg_addr, addr & 0x7fffffff); \
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__asm__ __volatile__("sync"); \
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return 0; \
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}
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PCI_OP(read, byte, u8 *, in_8, 3)
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PCI_OP(read, word, u16 *, in_le16, 2)
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PCI_OP(write, byte, u8, out_8, 3)
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PCI_OP(write, word, u16, out_le16, 2)
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PCI_OP(write, dword, u32, out_le32, 0)
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int mpc8220_pci_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
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int offset, u32 *val)
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{
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u32 addr;
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u32 tmpv;
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u32 mask = 2; /* word access */
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/* Read lower 16 bits */
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addr = ((offset & 0xfc) | (dev) | 0x80000000);
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out_be32(hose->cfg_addr, addr);
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__asm__ __volatile__("sync");
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*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
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out_be32(hose->cfg_addr, addr & 0x7fffffff);
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__asm__ __volatile__("sync");
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/* Read upper 16 bits */
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offset += 2;
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addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
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out_be32(hose->cfg_addr, addr);
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__asm__ __volatile__("sync");
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tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
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out_be32(hose->cfg_addr, addr & 0x7fffffff);
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__asm__ __volatile__("sync");
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/* combine results into dword value */
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*val = (tmpv << 16) | *val;
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return 0;
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}
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void
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pci_mpc8220_init(struct pci_controller *hose)
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{
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u32 win0, win1, win2;
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volatile mpc8220_xcpci_t *xcpci =
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(volatile mpc8220_xcpci_t *) MMAP_XCPCI;
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volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
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win0 = (u32) CONFIG_PCI_MEM_PHYS;
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win1 = (u32) CONFIG_PCI_IO_PHYS;
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win2 = (u32) CONFIG_PCI_CFG_PHYS;
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/* Assert PCI reset */
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out_be32 (&xcpci->glb_stat_ctl, PCI_GLB_STAT_CTRL_PR);
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/* Disable prefetching but read-multiples will still prefetch */
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out_be32 (&xcpci->target_ctrl, 0x00000000);
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/* Initiator windows */
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out_be32 (&xcpci->init_win0, (win0 >> 16) | win0 | 0x003f0000);
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out_be32 (&xcpci->init_win1, ((win1 >> 16) | win1 ));
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out_be32 (&xcpci->init_win2, ((win2 >> 16) | win2 ));
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out_be32 (&xcpci->init_win_cfg,
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PCI_INIT_WIN_CFG_WIN0_CTRL_EN |
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PCI_INIT_WIN_CFG_WIN1_CTRL_EN | PCI_INIT_WIN_CFG_WIN1_CTRL_IO |
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PCI_INIT_WIN_CFG_WIN2_CTRL_EN | PCI_INIT_WIN_CFG_WIN2_CTRL_IO);
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out_be32 (&xcpci->init_ctrl, 0x00000000);
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/* Enable bus master and mem access */
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out_be32 (&xcpci->stat_cmd_reg, PCI_STAT_CMD_B | PCI_STAT_CMD_M);
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/* Cache line size and master latency */
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out_be32 (&xcpci->bist_htyp_lat_cshl, (0xf8 << PCI_CFG1_LT_SHIFT));
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out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */
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out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */
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out_be32 (&xcpci->target_bar0,
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PCI_TARGET_BASE_ADDR_REG0 | PCI_TARGET_BASE_ADDR_EN);
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out_be32 (&xcpci->target_bar1,
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PCI_TARGET_BASE_ADDR_REG1 | PCI_TARGET_BASE_ADDR_EN);
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/* Deassert reset bit */
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out_be32 (&xcpci->glb_stat_ctl, 0x00000000);
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/* Enable PCI bus master support */
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/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
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PCIREQ2, PCIGNT2 */
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out_be32((volatile u32 *)&portcfg->pcfg3,
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(in_be32((volatile u32 *)&portcfg->pcfg3) & 0xFC3FCE7F));
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out_be32((volatile u32 *)&portcfg->pcfg3,
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(in_be32((volatile u32 *)&portcfg->pcfg3) | 0x01400180));
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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pci_set_region(hose->regions + 0,
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CONFIG_PCI_MEM_BUS,
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CONFIG_PCI_MEM_PHYS,
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CONFIG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 1,
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CONFIG_PCI_IO_BUS,
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CONFIG_PCI_IO_PHYS,
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CONFIG_PCI_IO_SIZE,
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PCI_REGION_IO);
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pci_set_region(hose->regions + 2,
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CONFIG_PCI_SYS_MEM_BUS,
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CONFIG_PCI_SYS_MEM_PHYS,
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CONFIG_PCI_SYS_MEM_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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hose->region_count = 3;
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hose->cfg_addr = &(xcpci->cfg_adr);
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hose->cfg_data = (volatile unsigned char *)CONFIG_PCI_CFG_BUS;
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pci_set_ops(hose,
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mpc8220_pci_read_config_byte,
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mpc8220_pci_read_config_word,
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mpc8220_pci_read_config_dword,
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mpc8220_pci_write_config_byte,
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mpc8220_pci_write_config_word,
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mpc8220_pci_write_config_dword);
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/* Hose scan */
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */
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out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */
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}
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#endif /* CONFIG_PCI */
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