mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-01 15:53:46 +09:00
e0059eaef1
The Samsung's UDC driver is not anymore copying data from USB requests to aligned internal buffers. Now it works directly in data allocated in the upper layers like UMS, DFU, THOR. This change is possible since those gadgets now must take care to allocate buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE). This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer aligned to cache line in both starting address and its size. Sometimes it is enough to just use memalign() with size being a multiplication of cache line size. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 27.04 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
112 lines
2.5 KiB
C
112 lines
2.5 KiB
C
/*
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* drivers/usb/gadget/s3c_udc.h
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* Samsung S3C on-chip full/high speed USB device controllers
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* Copyright (C) 2005 for Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __S3C_USB_GADGET
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#define __S3C_USB_GADGET
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#include <asm/errno.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/list.h>
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#include <usb/lin_gadget_compat.h>
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#define PHY0_SLEEP (1 << 5)
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/*-------------------------------------------------------------------------*/
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/* DMA bounce buffer size, 16K is enough even for mass storage */
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#define DMA_BUFFER_SIZE (16*SZ_1K)
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#define EP0_FIFO_SIZE 64
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#define EP_FIFO_SIZE 512
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#define EP_FIFO_SIZE2 1024
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/* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */
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#define S3C_MAX_ENDPOINTS 4
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#define S3C_MAX_HW_ENDPOINTS 16
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#define WAIT_FOR_SETUP 0
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#define DATA_STATE_XMIT 1
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#define DATA_STATE_NEED_ZLP 2
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#define WAIT_FOR_OUT_STATUS 3
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#define DATA_STATE_RECV 4
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#define WAIT_FOR_COMPLETE 5
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#define WAIT_FOR_OUT_COMPLETE 6
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#define WAIT_FOR_IN_COMPLETE 7
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#define WAIT_FOR_NULL_COMPLETE 8
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#define TEST_J_SEL 0x1
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#define TEST_K_SEL 0x2
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#define TEST_SE0_NAK_SEL 0x3
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#define TEST_PACKET_SEL 0x4
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#define TEST_FORCE_ENABLE_SEL 0x5
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/* ************************************************************************* */
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/* IO
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*/
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enum ep_type {
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ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
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};
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struct s3c_ep {
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struct usb_ep ep;
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struct s3c_udc *dev;
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const struct usb_endpoint_descriptor *desc;
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struct list_head queue;
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unsigned long pio_irqs;
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int len;
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void *dma_buf;
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u8 stopped;
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u8 bEndpointAddress;
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u8 bmAttributes;
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enum ep_type ep_type;
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int fifo_num;
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};
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struct s3c_request {
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struct usb_request req;
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struct list_head queue;
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};
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struct s3c_udc {
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct s3c_plat_otg_data *pdata;
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int ep0state;
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struct s3c_ep ep[S3C_MAX_ENDPOINTS];
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unsigned char usb_address;
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unsigned req_pending:1, req_std:1;
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};
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extern struct s3c_udc *the_controller;
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#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN) == USB_DIR_IN)
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#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
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#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
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extern void otg_phy_init(struct s3c_udc *dev);
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extern void otg_phy_off(struct s3c_udc *dev);
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extern void s3c_udc_ep_set_stall(struct s3c_ep *ep);
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extern int s3c_udc_probe(struct s3c_plat_otg_data *pdata);
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struct s3c_plat_otg_data {
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int (*phy_control)(int on);
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unsigned int regs_phy;
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unsigned int regs_otg;
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unsigned int usb_phy_ctrl;
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unsigned int usb_flags;
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};
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#endif
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