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https://github.com/brain-hackers/u-boot-brain
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379b3280b3
ARC core could be configured with different L1 and L2 (AKA SLC) cache line lengths. At least these values are possible and were really used: 32, 64 or 128 bytes. Current implementation requires cache line to be selected upon U-Boot configuration and then it will only work on matching hardware. Indeed this is quite efficient because cache line length gets hardcoded during code compilation. But OTOH it makes binary less portable. With this commit we allow U-Boot to determine real L1 cache line length early in runtime and use this value later on. This extends portability of U-Boot binary a lot. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
37 lines
860 B
C
37 lines
860 B
C
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARC_CACHE_H
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#define __ASM_ARC_CACHE_H
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#include <config.h>
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/*
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* As of today we may handle any L1 cache line length right in software.
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* For that essentially cache line length is a variable not constant.
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* And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length
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* that may exist in either L1 or L2 (AKA SLC) caches on ARC.
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*/
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#define ARCH_DMA_MINALIGN 128
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#if defined(ARC_MMU_ABSENT)
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#define CONFIG_ARC_MMU_VER 0
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#elif defined(CONFIG_ARC_MMU_V2)
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#define CONFIG_ARC_MMU_VER 2
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#elif defined(CONFIG_ARC_MMU_V3)
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#define CONFIG_ARC_MMU_VER 3
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#elif defined(CONFIG_ARC_MMU_V4)
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#define CONFIG_ARC_MMU_VER 4
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#endif
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#ifndef __ASSEMBLY__
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void cache_init(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARC_CACHE_H */
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