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![Chris Zankel](/assets/img/avatar_default.png)
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
11 lines
221 B
Makefile
11 lines
221 B
Makefile
#
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# (C) Copyright 2007 - 2013 Tensilica Inc.
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# (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_CMD_BOOTM) += bootm.o
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obj-y += cache.o misc.o relocate.o time.o
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