mirror of
https://github.com/brain-hackers/u-boot-brain
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![Bin Meng](/assets/img/avatar_default.png)
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
416 lines
9.7 KiB
C
416 lines
9.7 KiB
C
/*
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* U-Boot - cpu.c CPU specific functions
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <command.h>
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#include <serial.h>
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#include <version.h>
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#include <i2c.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/clock.h>
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#include <asm/mach-common/bits/core.h>
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#include <asm/mach-common/bits/ebiu.h>
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#include <asm/mach-common/bits/trace.h>
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#include "cpu.h"
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#include "initcode.h"
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#include "exports.h"
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ulong bfin_poweron_retx;
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
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void bfin_core1_start(void)
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{
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#ifdef BF561_FAMILY
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/* Enable core 1 */
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bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
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#else
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/* Enable core 1 */
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bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START);
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bfin_write32(RCU0_CRCTL, 0);
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bfin_write32(RCU0_CRCTL, 0x2);
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/* Check if core 1 starts */
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while (!(bfin_read32(RCU0_CRSTAT) & 0x2))
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continue;
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bfin_write32(RCU0_CRCTL, 0);
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/* flag to notify cces core 1 application */
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bfin_write32(SDU0_MSG_SET, (1 << 19));
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#endif
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}
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#endif
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__attribute__((always_inline))
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static inline void serial_early_puts(const char *s)
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{
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#ifdef CONFIG_DEBUG_EARLY_SERIAL
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serial_puts("Early: ");
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serial_puts(s);
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#endif
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}
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static int global_board_data_init(void)
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{
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#ifndef CONFIG_SYS_GBL_DATA_ADDR
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# define CONFIG_SYS_GBL_DATA_ADDR 0
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#endif
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#ifndef CONFIG_SYS_BD_INFO_ADDR
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# define CONFIG_SYS_BD_INFO_ADDR 0
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#endif
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bd_t *bd;
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if (CONFIG_SYS_GBL_DATA_ADDR) {
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gd = (gd_t *)(CONFIG_SYS_GBL_DATA_ADDR);
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memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
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} else {
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static gd_t _bfin_gd;
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gd = &_bfin_gd;
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}
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if (CONFIG_SYS_BD_INFO_ADDR) {
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bd = (bd_t *)(CONFIG_SYS_BD_INFO_ADDR);
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memset(bd, 0, GENERATED_BD_INFO_SIZE);
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} else {
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static bd_t _bfin_bd;
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bd = &_bfin_bd;
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}
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gd->bd = bd;
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bd->bi_r_version = version_string;
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bd->bi_cpu = __stringify(CONFIG_BFIN_CPU);
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bd->bi_board_name = CONFIG_SYS_BOARD;
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bd->bi_vco = get_vco();
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bd->bi_cclk = get_cclk();
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bd->bi_sclk = get_sclk();
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bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
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gd->ram_size = CONFIG_SYS_MAX_RAM_SIZE;
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return 0;
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}
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static void display_global_data(void)
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{
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bd_t *bd;
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#ifndef CONFIG_DEBUG_EARLY_SERIAL
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return;
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#endif
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bd = gd->bd;
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printf(" gd: %p\n", gd);
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printf(" |-flags: %lx\n", gd->flags);
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printf(" |-board_type: %lx\n", gd->arch.board_type);
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printf(" |-baudrate: %u\n", gd->baudrate);
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printf(" |-have_console: %lx\n", gd->have_console);
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printf(" |-ram_size: %lx\n", gd->ram_size);
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printf(" |-env_addr: %lx\n", gd->env_addr);
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printf(" |-env_valid: %lx\n", gd->env_valid);
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printf(" |-jt(%p): %p\n", gd->jt, gd->jt->get_version);
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printf(" \\-bd: %p\n", gd->bd);
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printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params);
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printf(" |-bi_memstart: %lx\n", bd->bi_memstart);
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printf(" |-bi_memsize: %lx\n", bd->bi_memsize);
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printf(" |-bi_flashstart: %lx\n", bd->bi_flashstart);
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printf(" |-bi_flashsize: %lx\n", bd->bi_flashsize);
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printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
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}
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#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
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#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
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#if defined(__ADSPBF60x__)
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#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024)
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#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1))
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#else
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#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE
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#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK
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#endif
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void init_cplbtables(void)
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{
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uint32_t *ICPLB_ADDR, *ICPLB_DATA;
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uint32_t *DCPLB_ADDR, *DCPLB_DATA;
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uint32_t extern_memory;
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size_t i;
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void icplb_add(uint32_t addr, uint32_t data)
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{
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bfin_write32(ICPLB_ADDR + i, addr);
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bfin_write32(ICPLB_DATA + i, data);
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}
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void dcplb_add(uint32_t addr, uint32_t data)
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{
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bfin_write32(DCPLB_ADDR + i, addr);
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bfin_write32(DCPLB_DATA + i, data);
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}
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/* populate a few common entries ... we'll let
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* the memory map and cplb exception handler do
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* the rest of the work.
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*/
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i = 0;
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ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0;
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ICPLB_DATA = (uint32_t *)ICPLB_DATA0;
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DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0;
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DCPLB_DATA = (uint32_t *)DCPLB_DATA0;
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icplb_add(0xFFA00000, L1_IMEMORY);
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dcplb_add(0xFF800000, L1_DMEMORY);
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++i;
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#if defined(__ADSPBF60x__)
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icplb_add(0x0, 0x0);
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dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
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CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
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++i;
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#endif
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if (CONFIG_MEM_SIZE) {
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uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
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uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN - 1;
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mbase &= CPLB_PAGE_MASK;
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mend &= CPLB_PAGE_MASK;
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icplb_add(mbase, SDRAM_IKERNEL);
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dcplb_add(mbase, SDRAM_DKERNEL);
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++i;
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/*
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* If the monitor crosses a 4 meg boundary, we'll need
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* to lock two entries for it. We assume it doesn't
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* cross two 4 meg boundaries ...
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*/
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if (mbase != mend) {
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icplb_add(mend, SDRAM_IKERNEL);
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dcplb_add(mend, SDRAM_DKERNEL);
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++i;
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}
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}
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#ifndef __ADSPBF60x__
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icplb_add(0x20000000, SDRAM_INON_CHBL);
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dcplb_add(0x20000000, SDRAM_EBIU);
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++i;
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#endif
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/* Add entries for the rest of external RAM up to the bootrom */
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extern_memory = 0;
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#ifdef CONFIG_DEBUG_NULL_PTR
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icplb_add(extern_memory,
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(SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
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dcplb_add(extern_memory,
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(SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
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++i;
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icplb_add(extern_memory, SDRAM_IKERNEL);
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dcplb_add(extern_memory, SDRAM_DKERNEL);
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extern_memory += CPLB_PAGE_SIZE;
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++i;
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#endif
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while (i < 16 && extern_memory <
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(CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) {
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icplb_add(extern_memory, SDRAM_IGENERIC);
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dcplb_add(extern_memory, SDRAM_DGENERIC);
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extern_memory += CPLB_EX_PAGE_SIZE;
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++i;
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}
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while (i < 16) {
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icplb_add(0, 0);
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dcplb_add(0, 0);
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++i;
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}
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}
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int print_cpuinfo(void)
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{
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char buf[32];
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printf("CPU: ADSP %s (Detected Rev: 0.%d) (%s boot)\n",
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gd->bd->bi_cpu,
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bfin_revid(),
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get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE));
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printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco()));
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printf("Core: %s MHz, ", strmhz(buf, get_cclk()));
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#if defined(__ADSPBF60x__)
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printf("System0: %s MHz, ", strmhz(buf, get_sclk0()));
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printf("System1: %s MHz, ", strmhz(buf, get_sclk1()));
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printf("Dclk: %s MHz\n", strmhz(buf, get_dclk()));
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#else
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printf("System: %s MHz\n", strmhz(buf, get_sclk()));
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#endif
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return 0;
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}
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int exception_init(void)
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{
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bfin_write_EVT3(trap);
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return 0;
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}
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int irq_init(void)
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{
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#ifdef SIC_IMASK0
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bfin_write_SIC_IMASK0(0);
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bfin_write_SIC_IMASK1(0);
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# ifdef SIC_IMASK2
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bfin_write_SIC_IMASK2(0);
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# endif
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#elif defined(SICA_IMASK0)
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bfin_write_SICA_IMASK0(0);
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bfin_write_SICA_IMASK1(0);
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#elif defined(SIC_IMASK)
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bfin_write_SIC_IMASK(0);
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#endif
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/* Set up a dummy NMI handler if needed. */
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if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
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bfin_write_EVT2(evt_nmi); /* NMI */
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bfin_write_EVT5(evt_default); /* hardware error */
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bfin_write_EVT6(evt_default); /* core timer */
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bfin_write_EVT7(evt_default);
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bfin_write_EVT8(evt_default);
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bfin_write_EVT9(evt_default);
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bfin_write_EVT10(evt_default);
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bfin_write_EVT11(evt_default);
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bfin_write_EVT12(evt_default);
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bfin_write_EVT13(evt_default);
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bfin_write_EVT14(evt_default);
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bfin_write_EVT15(evt_default);
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bfin_write_ILAT(0);
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CSYNC();
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/* enable hardware error irq */
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irq_flags = 0x3f;
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local_irq_enable();
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return 0;
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}
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__attribute__ ((__noreturn__))
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void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
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{
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#ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
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/* Build a NOP slide over the LDR jump block. Whee! */
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char nops[0xC];
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serial_early_puts("NOP Slide\n");
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memset(nops, 0x00, sizeof(nops));
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memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
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#endif
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if (!loaded_from_ldr) {
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/* Relocate sections into L1 if the LDR didn't do it -- don't
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* check length because the linker script does the size
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* checking at build time.
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*/
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serial_early_puts("L1 Relocate\n");
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extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
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memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
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extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
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memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
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}
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/*
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* Make sure our async settings are committed. Some bootroms
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* (like the BF537) will reset some registers on us after it
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* has finished loading the LDR. Or if we're booting over
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* JTAG, the initcode never got a chance to run. Or if we
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* aren't booting from parallel flash, the initcode skipped
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* this step completely.
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*/
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program_async_controller(NULL);
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/* Save RETX so we can pass it while booting Linux */
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bfin_poweron_retx = bootflag;
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#ifdef CONFIG_DEBUG_DUMP
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/* Turn on hardware trace buffer */
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bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
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#endif
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#ifndef CONFIG_PANIC_HANG
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/* Reset upon a double exception rather than just hanging.
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* Do not do bfin_read on SWRST as that will reset status bits.
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*/
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# ifdef SWRST
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bfin_write_SWRST(DOUBLE_FAULT);
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# endif
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#endif
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#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
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bfin_core1_start();
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#endif
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serial_early_puts("Init global data\n");
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global_board_data_init();
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board_init_f(0);
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/* should not be reached */
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while (1);
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}
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int arch_cpu_init(void)
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{
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serial_early_puts("Init CPLB tables\n");
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init_cplbtables();
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serial_early_puts("Exceptions setup\n");
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exception_init();
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#ifndef CONFIG_ICACHE_OFF
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serial_early_puts("Turn on ICACHE\n");
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icache_enable();
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#endif
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#ifndef CONFIG_DCACHE_OFF
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serial_early_puts("Turn on DCACHE\n");
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dcache_enable();
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#endif
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#ifdef DEBUG
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if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
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hang();
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#endif
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/* Initialize */
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serial_early_puts("IRQ init\n");
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irq_init();
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return 0;
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}
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int arch_misc_init(void)
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{
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#if defined(CONFIG_SYS_I2C)
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i2c_reloc_fixup();
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#endif
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display_global_data();
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if (CONFIG_MEM_SIZE && bfin_os_log_check()) {
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puts("\nLog buffer from operating system:\n");
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bfin_os_log_dump();
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puts("\n");
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}
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return 0;
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}
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int interrupt_init(void)
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{
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return 0;
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}
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