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![Johannes Krottmayer](/assets/img/avatar_default.png)
Add support for the RK3328 SPI controller Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
570 lines
15 KiB
C
570 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* spi driver for rockchip
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*
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* (C) 2019 Theobroma Systems Design und Consulting GmbH
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*
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* (C) Copyright 2015 Google, Inc
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*
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* (C) Copyright 2008-2013 Rockchip Electronics
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* Peter, Software Engineering, <superpeter.cai@gmail.com>.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <log.h>
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#include <spi.h>
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#include <time.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/periph.h>
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#include <dm/pinctrl.h>
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#include "rk_spi.h"
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/* Change to 1 to output registers at the start of each transaction */
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#define DEBUG_RK_SPI 0
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/*
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* ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
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* the controller seems to hang when given 0x10000, so stick with this for now.
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*/
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#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
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struct rockchip_spi_params {
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/* RXFIFO overruns and TXFIFO underruns stop the master clock */
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bool master_manages_fifo;
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};
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struct rockchip_spi_platdata {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3288_spi of_plat;
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#endif
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s32 frequency; /* Default clock frequency, -1 for none */
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fdt_addr_t base;
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uint deactivate_delay_us; /* Delay to wait after deactivate */
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uint activate_delay_us; /* Delay to wait after activate */
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};
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struct rockchip_spi_priv {
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struct rockchip_spi *regs;
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struct clk clk;
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unsigned int max_freq;
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unsigned int mode;
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ulong last_transaction_us; /* Time of last transaction end */
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unsigned int speed_hz;
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unsigned int last_speed_hz;
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uint input_rate;
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};
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#define SPI_FIFO_DEPTH 32
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static void rkspi_dump_regs(struct rockchip_spi *regs)
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{
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debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
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debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
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debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
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debug("ser: \t\t0x%08x\n", readl(®s->ser));
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debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
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debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
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debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
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debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
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debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
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debug("sr: \t\t0x%08x\n", readl(®s->sr));
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debug("imr: \t\t0x%08x\n", readl(®s->imr));
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debug("isr: \t\t0x%08x\n", readl(®s->isr));
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debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
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debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
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debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
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}
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static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
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{
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writel(enable ? 1 : 0, ®s->enr);
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}
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static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
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{
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/*
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* We should try not to exceed the speed requested by the caller:
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* when selecting a divider, we need to make sure we round up.
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*/
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uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
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/* The baudrate register (BAUDR) is defined as a 32bit register where
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* the upper 16bit are reserved and having 'Fsclk_out' in the lower
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* 16bits with 'Fsclk_out' defined as follows:
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*
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* Fsclk_out = Fspi_clk/ SCKDV
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* Where SCKDV is any even value between 2 and 65534.
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*/
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if (clk_div > 0xfffe) {
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clk_div = 0xfffe;
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debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
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__func__, speed, priv->input_rate / clk_div);
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}
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/* Round up to the next even 16bit number */
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clk_div = (clk_div + 1) & 0xfffe;
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debug("spi speed %u, div %u\n", speed, clk_div);
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clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
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priv->last_speed_hz = speed;
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}
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static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
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{
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unsigned long start;
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start = get_timer(0);
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while (readl(®s->sr) & SR_BUSY) {
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if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
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debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static void spi_cs_activate(struct udevice *dev, uint cs)
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{
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struct udevice *bus = dev->parent;
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struct rockchip_spi_platdata *plat = bus->platdata;
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struct rockchip_spi_priv *priv = dev_get_priv(bus);
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struct rockchip_spi *regs = priv->regs;
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/* If it's too soon to do another transaction, wait */
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if (plat->deactivate_delay_us && priv->last_transaction_us) {
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ulong delay_us; /* The delay completed so far */
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delay_us = timer_get_us() - priv->last_transaction_us;
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if (delay_us < plat->deactivate_delay_us) {
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ulong additional_delay_us =
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plat->deactivate_delay_us - delay_us;
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debug("%s: delaying by %ld us\n",
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__func__, additional_delay_us);
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udelay(additional_delay_us);
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}
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}
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debug("activate cs%u\n", cs);
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writel(1 << cs, ®s->ser);
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if (plat->activate_delay_us)
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udelay(plat->activate_delay_us);
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}
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static void spi_cs_deactivate(struct udevice *dev, uint cs)
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{
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struct udevice *bus = dev->parent;
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struct rockchip_spi_platdata *plat = bus->platdata;
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struct rockchip_spi_priv *priv = dev_get_priv(bus);
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struct rockchip_spi *regs = priv->regs;
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debug("deactivate cs%u\n", cs);
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writel(0, ®s->ser);
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/* Remember time of this transaction so we can honour the bus delay */
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if (plat->deactivate_delay_us)
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priv->last_transaction_us = timer_get_us();
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}
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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static int conv_of_platdata(struct udevice *dev)
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{
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struct rockchip_spi_platdata *plat = dev->platdata;
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struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
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struct rockchip_spi_priv *priv = dev_get_priv(dev);
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int ret;
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plat->base = dtplat->reg[0];
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plat->frequency = 20000000;
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ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
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if (ret < 0)
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return ret;
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dev->req_seq = 0;
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return 0;
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}
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#endif
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static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
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struct rockchip_spi_priv *priv = dev_get_priv(bus);
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int ret;
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plat->base = dev_read_addr(bus);
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ret = clk_get_by_index(bus, 0, &priv->clk);
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if (ret < 0) {
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debug("%s: Could not get clock for %s: %d\n", __func__,
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bus->name, ret);
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return ret;
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}
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plat->frequency =
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dev_read_u32_default(bus, "spi-max-frequency", 50000000);
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plat->deactivate_delay_us =
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dev_read_u32_default(bus, "spi-deactivate-delay", 0);
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plat->activate_delay_us =
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dev_read_u32_default(bus, "spi-activate-delay", 0);
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debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
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__func__, (uint)plat->base, plat->frequency,
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plat->deactivate_delay_us);
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#endif
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return 0;
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}
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static int rockchip_spi_calc_modclk(ulong max_freq)
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{
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/*
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* While this is not strictly correct for the RK3368, as the
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* GPLL will be 576MHz, things will still work, as the
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* clk_set_rate(...) implementation in our clock-driver will
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* chose the next closest rate not exceeding what we request
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* based on the output of this function.
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*/
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unsigned div;
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const unsigned long gpll_hz = 594000000UL;
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/*
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* We need to find an input clock that provides at least twice
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* the maximum frequency and can be generated from the assumed
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* speed of GPLL (594MHz) using an integer divider.
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*
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* To give us more achievable bitrates at higher speeds (these
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* are generated by dividing by an even 16-bit integer from
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* this frequency), we try to have an input frequency of at
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* least 4x our max_freq.
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*/
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div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
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return gpll_hz / div;
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}
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static int rockchip_spi_probe(struct udevice *bus)
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{
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struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
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struct rockchip_spi_priv *priv = dev_get_priv(bus);
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int ret;
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debug("%s: probe\n", __func__);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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ret = conv_of_platdata(bus);
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if (ret)
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return ret;
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#endif
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priv->regs = (struct rockchip_spi *)plat->base;
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priv->last_transaction_us = timer_get_us();
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priv->max_freq = plat->frequency;
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/* Clamp the value from the DTS against any hardware limits */
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if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
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priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
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/* Find a module-input clock that fits with the max_freq setting */
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ret = clk_set_rate(&priv->clk,
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rockchip_spi_calc_modclk(priv->max_freq));
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if (ret < 0) {
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debug("%s: Failed to set clock: %d\n", __func__, ret);
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return ret;
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}
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priv->input_rate = ret;
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debug("%s: rate = %u\n", __func__, priv->input_rate);
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return 0;
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}
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static int rockchip_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct rockchip_spi_priv *priv = dev_get_priv(bus);
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struct rockchip_spi *regs = priv->regs;
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uint ctrlr0;
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/* Disable the SPI hardware */
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rkspi_enable_chip(regs, false);
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if (priv->speed_hz != priv->last_speed_hz)
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rkspi_set_clk(priv, priv->speed_hz);
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/* Operation Mode */
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ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
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/* Data Frame Size */
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ctrlr0 |= DFS_8BIT << DFS_SHIFT;
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/* set SPI mode 0..3 */
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if (priv->mode & SPI_CPOL)
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ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
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if (priv->mode & SPI_CPHA)
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ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
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/* Chip Select Mode */
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ctrlr0 |= CSM_KEEP << CSM_SHIFT;
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/* SSN to Sclk_out delay */
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ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
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/* Serial Endian Mode */
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ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
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/* First Bit Mode */
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ctrlr0 |= FBM_MSB << FBM_SHIFT;
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/* Byte and Halfword Transform */
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ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
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/* Rxd Sample Delay */
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ctrlr0 |= 0 << RXDSD_SHIFT;
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/* Frame Format */
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ctrlr0 |= FRF_SPI << FRF_SHIFT;
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/* Tx and Rx mode */
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ctrlr0 |= TMOD_TR << TMOD_SHIFT;
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writel(ctrlr0, ®s->ctrlr0);
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return 0;
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}
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static int rockchip_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct rockchip_spi_priv *priv = dev_get_priv(bus);
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rkspi_enable_chip(priv->regs, false);
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return 0;
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}
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static inline int rockchip_spi_16bit_reader(struct udevice *dev,
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u8 **din, int *len)
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{
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struct udevice *bus = dev->parent;
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const struct rockchip_spi_params * const data =
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(void *)dev_get_driver_data(bus);
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struct rockchip_spi_priv *priv = dev_get_priv(bus);
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struct rockchip_spi *regs = priv->regs;
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const u32 saved_ctrlr0 = readl(®s->ctrlr0);
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#if defined(DEBUG)
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u32 statistics_rxlevels[33] = { };
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#endif
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u32 frames = *len / 2;
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u8 *in = (u8 *)(*din);
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u32 max_chunk_size = SPI_FIFO_DEPTH;
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if (!frames)
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return 0;
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/*
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* If we know that the hardware will manage RXFIFO overruns
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* (i.e. stop the SPI clock until there's space in the FIFO),
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* we the allow largest possible chunk size that can be
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* represented in CTRLR1.
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*/
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if (data && data->master_manages_fifo)
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max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
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// rockchip_spi_configure(dev, mode, size)
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rkspi_enable_chip(regs, false);
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clrsetbits_le32(®s->ctrlr0,
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TMOD_MASK << TMOD_SHIFT,
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TMOD_RO << TMOD_SHIFT);
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/* 16bit data frame size */
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clrsetbits_le32(®s->ctrlr0, DFS_MASK, DFS_16BIT);
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/* Update caller's context */
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const u32 bytes_to_process = 2 * frames;
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*din += bytes_to_process;
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*len -= bytes_to_process;
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/* Process our frames */
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while (frames) {
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u32 chunk_size = min(frames, max_chunk_size);
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frames -= chunk_size;
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writew(chunk_size - 1, ®s->ctrlr1);
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rkspi_enable_chip(regs, true);
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do {
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u32 rx_level = readw(®s->rxflr);
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#if defined(DEBUG)
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statistics_rxlevels[rx_level]++;
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#endif
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chunk_size -= rx_level;
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while (rx_level--) {
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u16 val = readw(regs->rxdr);
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*in++ = val & 0xff;
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*in++ = val >> 8;
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}
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} while (chunk_size);
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rkspi_enable_chip(regs, false);
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}
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#if defined(DEBUG)
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debug("%s: observed rx_level during processing:\n", __func__);
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for (int i = 0; i <= 32; ++i)
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if (statistics_rxlevels[i])
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debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
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#endif
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/* Restore the original transfer setup and return error-free. */
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writel(saved_ctrlr0, ®s->ctrlr0);
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return 0;
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}
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static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct rockchip_spi_priv *priv = dev_get_priv(bus);
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struct rockchip_spi *regs = priv->regs;
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struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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int len = bitlen >> 3;
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const u8 *out = dout;
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u8 *in = din;
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int toread, towrite;
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int ret = 0;
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debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
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len, flags);
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if (DEBUG_RK_SPI)
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rkspi_dump_regs(regs);
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/* Assert CS before transfer */
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(dev, slave_plat->cs);
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/*
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* To ensure fast loading of firmware images (e.g. full U-Boot
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* stage, ATF, Linux kernel) from SPI flash, we optimise the
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* case of read-only transfers by using the full 16bits of each
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* FIFO element.
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*/
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if (!out)
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ret = rockchip_spi_16bit_reader(dev, &in, &len);
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/* This is the original 8bit reader/writer code */
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while (len > 0) {
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int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
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rkspi_enable_chip(regs, false);
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writel(todo - 1, ®s->ctrlr1);
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rkspi_enable_chip(regs, true);
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toread = todo;
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towrite = todo;
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while (toread || towrite) {
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u32 status = readl(®s->sr);
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if (towrite && !(status & SR_TF_FULL)) {
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writel(out ? *out++ : 0, regs->txdr);
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towrite--;
|
|
}
|
|
if (toread && !(status & SR_RF_EMPT)) {
|
|
u32 byte = readl(regs->rxdr);
|
|
|
|
if (in)
|
|
*in++ = byte;
|
|
toread--;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* In case that there's a transmit-component, we need to wait
|
|
* until the control goes idle before we can disable the SPI
|
|
* control logic (as this will implictly flush the FIFOs).
|
|
*/
|
|
if (out) {
|
|
ret = rkspi_wait_till_not_busy(regs);
|
|
if (ret)
|
|
break;
|
|
}
|
|
|
|
len -= todo;
|
|
}
|
|
|
|
/* Deassert CS after transfer */
|
|
if (flags & SPI_XFER_END)
|
|
spi_cs_deactivate(dev, slave_plat->cs);
|
|
|
|
rkspi_enable_chip(regs, false);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
struct rockchip_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
/* Clamp to the maximum frequency specified in the DTS */
|
|
if (speed > priv->max_freq)
|
|
speed = priv->max_freq;
|
|
|
|
priv->speed_hz = speed;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
struct rockchip_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
priv->mode = mode;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_spi_ops rockchip_spi_ops = {
|
|
.claim_bus = rockchip_spi_claim_bus,
|
|
.release_bus = rockchip_spi_release_bus,
|
|
.xfer = rockchip_spi_xfer,
|
|
.set_speed = rockchip_spi_set_speed,
|
|
.set_mode = rockchip_spi_set_mode,
|
|
/*
|
|
* cs_info is not needed, since we require all chip selects to be
|
|
* in the device tree explicitly
|
|
*/
|
|
};
|
|
|
|
const struct rockchip_spi_params rk3399_spi_params = {
|
|
.master_manages_fifo = true,
|
|
};
|
|
|
|
static const struct udevice_id rockchip_spi_ids[] = {
|
|
{ .compatible = "rockchip,rk3066-spi" },
|
|
{ .compatible = "rockchip,rk3288-spi" },
|
|
{ .compatible = "rockchip,rk3328-spi" },
|
|
{ .compatible = "rockchip,rk3368-spi",
|
|
.data = (ulong)&rk3399_spi_params },
|
|
{ .compatible = "rockchip,rk3399-spi",
|
|
.data = (ulong)&rk3399_spi_params },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_rk3288_spi) = {
|
|
.name = "rockchip_rk3288_spi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = rockchip_spi_ids,
|
|
.ops = &rockchip_spi_ops,
|
|
.ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
|
|
.platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
|
|
.priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
|
|
.probe = rockchip_spi_probe,
|
|
};
|
|
|
|
U_BOOT_DRIVER_ALIAS(rockchip_rk3288_spi, rockchip_rk3368_spi)
|