mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 11:46:17 +09:00
df548d3c3e
Rewrite the resource management code (i.e. I/O memory, clock gating, gpio) so it doesn't depend on any global state. This is necessary because this code is heavily used before relocation to RAM, so we can't write to any global variables. As an added bonus, this makes u-boot's memory footprint a bit smaller, although some functionality has been left out; all clocks are enabled all the time, and there's no checking for gpio line conflicts. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
185 lines
5.0 KiB
C
185 lines
5.0 KiB
C
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* Configuration settings for the ATSTK1002 CPU daughterboard
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AVR32 1
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#define CONFIG_AT32AP 1
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#define CONFIG_AT32AP7000 1
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#define CONFIG_ATSTK1002 1
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#define CONFIG_ATSTK1000 1
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#define CONFIG_ATSTK1000_EXT_FLASH 1
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/*
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* Timer clock frequency. We're using the CPU-internal COUNT register
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* for this, so this is equivalent to the CPU core clock frequency
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*/
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#define CFG_HZ 1000
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/*
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* Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
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* frequency and the peripherals to run at 1/4 the PLL frequency.
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*/
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#define CONFIG_PLL 1
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#define CFG_POWER_MANAGER 1
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#define CFG_OSC0_HZ 20000000
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#define CFG_PLL0_DIV 1
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#define CFG_PLL0_MUL 7
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#define CFG_PLL0_SUPPRESS_CYCLES 16
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#define CFG_CLKDIV_CPU 0
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#define CFG_CLKDIV_HSB 1
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#define CFG_CLKDIV_PBA 2
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#define CFG_CLKDIV_PBB 1
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/*
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* The PLLOPT register controls the PLL like this:
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* icp = PLLOPT<2>
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* ivco = PLLOPT<1:0>
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*
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
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*/
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#define CFG_PLL0_OPT 0x04
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#undef CONFIG_USART0
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#define CONFIG_USART1 1
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#undef CONFIG_USART2
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#undef CONFIG_USART3
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/* User serviceable stuff */
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#define CONFIG_CMDLINE_TAG 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_STACKSIZE (2048)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS \
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"console=ttyUS0 root=/dev/mtdblock1 fbmem=600k"
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#define CONFIG_COMMANDS (CFG_CMD_BDI \
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| CFG_CMD_LOADS \
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| CFG_CMD_LOADB \
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/* | CFG_CMD_IMI */ \
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/* | CFG_CMD_CACHE */ \
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| CFG_CMD_FLASH \
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| CFG_CMD_MEMORY \
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/* | CFG_CMD_NET */ \
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| CFG_CMD_ENV \
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/* | CFG_CMD_IRQ */ \
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| CFG_CMD_BOOTD \
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| CFG_CMD_CONSOLE \
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/* | CFG_CMD_EEPROM */ \
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| CFG_CMD_ASKENV \
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| CFG_CMD_RUN \
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| CFG_CMD_ECHO \
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/* | CFG_CMD_I2C */ \
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| CFG_CMD_REGINFO \
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/* | CFG_CMD_DATE */ \
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/* | CFG_CMD_DHCP */ \
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/* | CFG_CMD_AUTOSCRIPT */ \
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/* | CFG_CMD_MII */ \
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| CFG_CMD_MISC \
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/* | CFG_CMD_SDRAM */ \
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/* | CFG_CMD_DIAG */ \
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/* | CFG_CMD_HWFLOW */ \
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/* | CFG_CMD_SAVES */ \
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/* | CFG_CMD_SPI */ \
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/* | CFG_CMD_PING */ \
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/* | CFG_CMD_MMC */ \
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/* | CFG_CMD_FAT */ \
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/* | CFG_CMD_IMLS */ \
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/* | CFG_CMD_ITEST */ \
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/* | CFG_CMD_EXT2 */ \
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)
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#include <cmd_confdefs.h>
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#define CONFIG_ATMEL_USART 1
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#define CONFIG_PIO2 1
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#define CFG_NR_PIOS 5
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#define CFG_HSDRAMC 1
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#define CFG_DCACHE_LINESZ 32
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#define CFG_ICACHE_LINESZ 32
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#define CONFIG_NR_DRAM_BANKS 1
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/* External flash on STK1000 */
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#if 0
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#define CFG_FLASH_CFI 1
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#define CFG_FLASH_CFI_DRIVER 1
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#endif
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#define CFG_FLASH_BASE 0x00000000
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#define CFG_FLASH_SIZE 0x800000
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 135
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_INTRAM_BASE 0x24000000
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#define CFG_INTRAM_SIZE 0x8000
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#define CFG_SDRAM_BASE 0x10000000
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SIZE 65536
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
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#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
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#define CFG_MALLOC_LEN (256*1024)
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#define CFG_MALLOC_END \
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({ \
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DECLARE_GLOBAL_DATA_PTR; \
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CFG_SDRAM_BASE + gd->sdram_size; \
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})
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#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN)
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#define CFG_DMA_ALLOC_LEN (16384)
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#define CFG_DMA_ALLOC_END (CFG_MALLOC_START)
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#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
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/* Allow 2MB for the kernel run-time image */
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#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
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#define CFG_BOOTPARAMS_LEN (16 * 1024)
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/* Other configuration settings that shouldn't have to change all that often */
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#define CFG_PROMPT "Uboot> "
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#define CFG_CBSIZE 256
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#define CFG_MAXARGS 8
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
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#define CFG_LONGHELP 1
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#define CFG_MEMTEST_START \
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({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
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#define CFG_MEMTEST_END \
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({ \
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DECLARE_GLOBAL_DATA_PTR; \
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gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
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})
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#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
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#endif /* __CONFIG_H */
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