mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-09 14:23:28 +09:00
df3443dfa4
On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed). This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Bryan Wu <pengw@nvidia.com> [acourbot: ensure write went through, vpr.c style changes] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <TWarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
77 lines
1.9 KiB
C
77 lines
1.9 KiB
C
/*
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* (C) Copyright 2010-2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/types.h>
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/* Stabilization delays, in usec */
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#define PLL_STABILIZATION_DELAY (300)
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#define IO_STABILIZATION_DELAY (1000)
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#define PLLX_ENABLED (1 << 30)
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#define CCLK_BURST_POLICY 0x20008888
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#define SUPER_CCLK_DIVIDER 0x80000000
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/* Calculate clock fractional divider value from ref and target frequencies */
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#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
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/* Calculate clock frequency value from reference and clock divider value */
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#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
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/* AVP/CPU ID */
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#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
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#define PG_UP_TAG_0 0x0
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#define CORESIGHT_UNLOCK 0xC5ACCE55;
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/* AP base physical address of internal SRAM */
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#define NV_PA_BASE_SRAM 0x40000000
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#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
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#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
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#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
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#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
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#define FLOW_MODE_STOP 2
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#define HALT_COP_EVENT_JTAG (1 << 28)
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#define HALT_COP_EVENT_IRQ_1 (1 << 11)
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#define HALT_COP_EVENT_FIQ_1 (1 << 9)
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/* This is the main entry into U-Boot, used by the Cortex-A9 */
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extern void _start(void);
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/**
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* Works out the SOC/SKU type used for clocks settings
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*
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* @return SOC type - see TEGRA_SOC...
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*/
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int tegra_get_chip_sku(void);
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/**
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* Returns the pure SOC (chip ID) from the HIDREV register
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*
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* @return SOC ID - see CHIPID_TEGRAxx...
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*/
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int tegra_get_chip(void);
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/**
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* Returns the SKU ID from the sku_info register
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*
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* @return SKU ID - see SKU_ID_Txx...
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*/
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int tegra_get_sku_info(void);
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/* Do any chip-specific cache config */
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void config_cache(void);
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#if defined(CONFIG_TEGRA124)
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/* Do chip-specific vpr config */
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void config_vpr(void);
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#else
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static inline void config_vpr(void)
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{
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}
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#endif
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