mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
821ad16fa9
The CONFIG_BFIN_CPU option is largely used in the build system, so move it out of the board config.h and into the board config.mk. It'd be nice to keep everything in the config.h, but the patch to extract that value early was rejected. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
130 lines
3.5 KiB
C
130 lines
3.5 KiB
C
/*
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* U-boot - Configuration file for IBF-DSP561 board
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*/
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#ifndef __CONFIG_IBF_DSP561__H__
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#define __CONFIG_IBF_DSP561__H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 25000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 24
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 5
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 9
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#define CONFIG_MEM_SIZE 64
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#define CONFIG_EBIU_SDRRC_VAL 0x377
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#define CONFIG_EBIU_SDGCTL_VAL 0x91998d
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#define CONFIG_EBIU_SDBCTL_VAL 0x15
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#define CONFIG_EBIU_AMGCTL_VAL 0x3F
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#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
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/*
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* Network Settings
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*/
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_NET_MULTI
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#define CONFIG_DRIVER_AX88180 1
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#define AX88180_BASE 0x2c000000
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#define CONFIG_HOSTNAME ibf-dsp561
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
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/*
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* Flash Settings
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*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI_AMD_RESET
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#define CONFIG_SYS_FLASH_BASE 0x20000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
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/* The BF561-EZKIT uses a top boot flash */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR 0x20004000
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
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#define ENV_IS_EMBEDDED
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#else
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#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
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#endif
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#ifdef ENV_IS_EMBEDDED
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/* WARNING - the following is hand-optimized to fit within
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* the sector before the environment sector. If it throws
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* an error during compilation remove an object here to get
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* it linked after the configuration sector.
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*/
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# define LDS_BOARD_TEXT \
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arch/blackfin/cpu/traps.o (.text .text.*); \
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arch/blackfin/cpu/interrupt.o (.text .text.*); \
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arch/blackfin/cpu/serial.o (.text .text.*); \
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common/dlmalloc.o (.text .text.*); \
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lib/crc32.o (.text .text.*); \
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lib/zlib.o (.text .text.*); \
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board/ibf-dsp561/ibf-dsp561.o (.text .text.*); \
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. = DEFINED(env_offset) ? env_offset : .; \
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common/env_embedded.o (.text .text.*);
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#endif
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/*
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* I2C Settings
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*/
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#define CONFIG_SOFT_I2C 1
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#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
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#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
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/*
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* Misc Settings
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*/
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#define CONFIG_UART_CONSOLE 0
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#endif
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