mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
d98b0523cf
Now that warm booting is not supported, there isn't a need for the BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them. Note that this change makes the board info bd_bootflags field useless. It will always be set to 0, but we leave it around so that we don't break the board info structure that some OSes are expecting to be passed from U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
428 lines
13 KiB
C
428 lines
13 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2002,2003 Motorola,Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* pm854 board configuration file
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*
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* Please refer to doc/README.mpc85xx for more info.
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*
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* Make sure you change the MAC address and other network params first,
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* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
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#define CONFIG_MPC8540 1 /* MPC8540 specific */
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#define CONFIG_PM854 1 /* PM854 board specific */
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#define CONFIG_SYS_TEXT_BASE 0xfff80000
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#define CONFIG_PCI
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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/*
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* sysclk for MPC85xx
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*
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* Two valid values are:
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* 33000000
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* 66000000
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*
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* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
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* is likely the desired value here, so that is now the default.
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* The board, however, can run at 66MHz. In any event, this value
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* must match the settings of some switches. Details can be found
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* in the README.mpc85xxads.
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*/
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 66000000
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#endif
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
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/* DDR Setup */
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#define CONFIG_FSL_DDR1
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#undef CONFIG_FSL_DDR_INTERACTIVE
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#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#undef CONFIG_DDR_SPD
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#define CONFIG_DDR_DLL /* possible DLL fix needed */
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#define CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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/* I2C addresses of SPD EEPROMs */
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#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */
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/* Manually set up DDR parameters */
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#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256 MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
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#define CONFIG_SYS_DDR_TIMING_1 0x47444321
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#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
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#define CONFIG_SYS_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
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#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
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#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
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/*
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* SDRAM on the Local Bus
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*/
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
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#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */
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#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */
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#define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */
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#define CONFIG_SYS_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
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#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
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#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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/*
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* I2C
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*/
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/*
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* RTC configuration
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*/
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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/* RapidIO MMU */
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#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
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#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
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#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
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#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
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#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
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#if defined(CONFIG_PCI)
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_EEPRO100
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#define CONFIG_E1000
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#undef CONFIG_TULIP
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#if !defined(CONFIG_PCI_PNP)
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#define PCI_ENET0_IOADDR 0xe0000000
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#define PCI_ENET0_MEMADDR 0xe0000000
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#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
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#endif
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define CONFIG_MPC85XX_FEC 1
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#define CONFIG_MPC85XX_FEC_NAME "FEC"
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#define FEC_PHY_ADDR 3
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#define FEC_PHYIDX 0
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#define FEC_FLAGS 0
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC0"
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1 1
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#define CONFIG_HAS_ETH2 1
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000)
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#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
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#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_REGINFO
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if defined(CONFIG_SYS_RAMBOOT)
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#undef CONFIG_CMD_SAVEENV
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#undef CONFIG_CMD_LOADS
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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#define CONFIG_LOOPW
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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/* The mac addresses for all ethernet interface */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_ETHADDR 00:40:42:01:00:00
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#define CONFIG_ETH1ADDR 00:40:42:01:00:01
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#define CONFIG_ETH2ADDR 00:40:42:01:00:02
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#endif
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#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
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#define CONFIG_BOOTFILE pm854/uImage
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#define CONFIG_HOSTNAME pm854
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#define CONFIG_IPADDR 192.168.0.103
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#define CONFIG_SERVERIP 192.168.0.64
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#define CONFIG_GATEWAYIP 192.168.0.1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
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#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=400000\0" \
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"ramdiskfile=pm854/uRamdisk\0"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"bootm $loadaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"bootm $loadaddr $ramdiskaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
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#endif /* __CONFIG_H */
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