mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
d98b0523cf
Now that warm booting is not supported, there isn't a need for the BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them. Note that this change makes the board info bd_bootflags field useless. It will always be set to 0, but we leave it around so that we don't break the board info structure that some OSes are expecting to be passed from U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
371 lines
15 KiB
C
371 lines
15 KiB
C
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_ERIC 1 /* ...on a ERIC board */
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* run board_early_init_f() */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#if 1
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#endif
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#if 0
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#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
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#endif
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#if 0
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#define CONFIG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */
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#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
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#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
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#endif /* total size of a X1240 is 2048 bytes */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */
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#define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x6F /* and one for RTC */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#undef CONFIG_ENV_IS_IN_NVRAM
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#undef CONFIG_ENV_IS_IN_EEPROM
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#else
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#ifdef CONFIG_ENV_IS_IN_NVRAM
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#undef CONFIG_ENV_IS_IN_FLASH
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#undef CONFIG_ENV_IS_IN_EEPROM
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#else
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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#undef CONFIG_ENV_IS_IN_NVRAM
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#undef CONFIG_ENV_IS_IN_FLASH
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#endif
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#endif
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#if 1
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#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
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#else
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#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
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#endif
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#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \
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"nfsroot=192.168.1.2:/eric_root_devel " \
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"ip=192.168.1.22:192.168.1.2"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* PHY address */
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#define CONFIG_NET_MULTI
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_FLASH
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#undef CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#define CONFIG_SYS_EXT_SERIAL_CLOCK 14318180
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#undef CONFIG_PCI_PNP /* no pci plug-and-play */
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/* resource configuration */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */
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#define CONFIG_SYS_PCI_PTM1LA 0xFFFC0000 /* point to flash */
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#define CONFIG_SYS_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* External peripheral base address
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*-----------------------------------------------------------------------
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*/
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/* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */
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/* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */
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/* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */
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/* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */
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/* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */
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/* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */
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/* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */
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/* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */
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/* ----------------------------------------------------------------------- */
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/* Memory Bank 0 (Flash) initialization */
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/* ----------------------------------------------------------------------- */
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#define CS0_AP 0x9B015480
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#define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
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/* ----------------------------------------------------------------------- */
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/* Memory Bank 1 (NVRAM/RTC) initialization */
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/* ----------------------------------------------------------------------- */
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#define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
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#define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
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/* ----------------------------------------------------------------------- */
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/* Memory Bank 2 (A/D converter) initialization */
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/* ----------------------------------------------------------------------- */
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#define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
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#define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
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/* ----------------------------------------------------------------------- */
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/* Memory Bank 3 (Ethernet PHY Reset) initialization */
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/* ----------------------------------------------------------------------- */
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#define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
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#define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
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/* ----------------------------------------------------------------------- */
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/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
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/* ----------------------------------------------------------------------- */
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#define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
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#define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
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/* ----------------------------------------------------------------------- */
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/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
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/* ----------------------------------------------------------------------- */
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#define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
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#define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
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/* ----------------------------------------------------------------------- */
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/* Memory Bank 6 (CPU LED0) initialization */
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/* ----------------------------------------------------------------------- */
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#define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
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#define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
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/* ----------------------------------------------------------------------- */
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/* Memory Bank 7 (CPU LED1) initialization */
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/* ----------------------------------------------------------------------- */
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#define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
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#define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
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#define CONFIG_SYS_NVRAM_REG_BASE_ADDR 0xF0000000
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#define CONFIG_SYS_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8)
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#define CONFIG_SYS_ADC_REG_BASE_ADDR 0xF0100000
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#define CONFIG_SYS_PHYRES_REG_BASE_ADDR 0xF0200000
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#define CONFIG_SYS_PRSNT1_REG_BASE_ADDR 0xF0300000
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#define CONFIG_SYS_PRSNT2_REG_BASE_ADDR 0xF0400000
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#define CONFIG_SYS_LED0_REG_BASE_ADDR 0xF0500000
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#define CONFIG_SYS_LED1_REG_BASE_ADDR 0xF0600000
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/* SDRAM CONFIG */
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#define CONFIG_SYS_SDRAM_MANUALLY 1
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#define CONFIG_SYS_SDRAM_SINGLE_BANK 1
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#ifdef CONFIG_SYS_SDRAM_MANUALLY
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/*-----------------------------------------------------------------------
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* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
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*----------------------------------------------------------------------*/
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#define MB0CF 0x00062001 /* 32MB @ 0 */
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/*-----------------------------------------------------------------------
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* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
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*----------------------------------------------------------------------*/
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#ifdef CONFIG_SYS_SDRAM_SINGLE_BANK
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#define MB1CF 0x0 /* 0MB @ 32MB */
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#else
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#define MB1CF 0x02062001 /* 32MB @ 32MB */
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#endif
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/*-----------------------------------------------------------------------
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* Set MB2CF for bank 2. off
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*----------------------------------------------------------------------*/
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#define MB2CF 0x0 /* 0MB */
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/*-----------------------------------------------------------------------
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* Set MB3CF for bank 3. off
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*----------------------------------------------------------------------*/
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#define MB3CF 0x0 /* 0MB */
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#define SDTR_100 0x0086400D
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#define RTR_100 0x05F0
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#define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */
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#define RTR_66 0x03f8
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#endif /* CONFIG_SYS_SDRAM_MANUALLY */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_SIZE 32
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#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* 8 MByte Flash */
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#define CONFIG_SYS_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */
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/*#define CONFIG_SYS_MONITOR_LEN (192 * 1024)*/ /* Reserve 196 kB for Monitor */
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_16BIT 1 /* Rom 16 bit data bus */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/* BEG ENVIRONNEMENT FLASH */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE (128*1024)
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#if 0 /* force ENV to be NOT embedded */
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#define CONFIG_ENV_ADDR 0xfffa0000
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#else /* force ENV to be embedded */
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#define CONFIG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
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/* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE)*/
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
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#endif
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#endif
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/* END ENVIRONNEMENT FLASH */
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/*-----------------------------------------------------------------------
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* NVRAM organization
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*/
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#define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_REG_BASE_ADDR /* NVRAM base address */
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#define CONFIG_SYS_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */
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#ifdef CONFIG_ENV_IS_IN_NVRAM
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#define CONFIG_ENV_SIZE 0x7F8 /* Size of Environment vars */
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
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#endif
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */
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#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
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/* Configuration Port location */
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/* #define CONFIG_PORT_ADDR 0xF0000500 */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
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#define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Definitions for Serial Presence Detect EEPROM address
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* (to get SDRAM settings)
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*/
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#define SPD_EEPROM_ADDRESS 0x50
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#endif /* __CONFIG_H */
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