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Add short documentation-alike note on how to use the Altera SPI driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V into doc/SPI/README.altera_spi Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
7 lines
278 B
Plaintext
7 lines
278 B
Plaintext
SoCFPGA EPCS/EPCQx1 mini howto:
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- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
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- The controller base address is the "Base" in QSys + 0x400
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- Set MSEL[4:0]=10010 (AS Standard)
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- Load the bitstream into FPGA, enable bridges
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- Only then will the driver work
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