mirror of
https://github.com/brain-hackers/u-boot-brain
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ccf8f824ef
We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you don't need to do Hit_Invalidate_I, but flush_cache() needs it since this function is used not only in U-Boot specfic programs but also at loading target binaries. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
77 lines
2.2 KiB
C
77 lines
2.2 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/inca-ip.h>
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#include <asm/mipsregs.h>
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#include <asm/cacheops.h>
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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#if defined(CONFIG_INCA_IP)
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*INCA_IP_WDT_RST_REQ = 0x3f;
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#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
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void (*f)(void) = (void *) 0xbfc00000;
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f();
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#endif
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fprintf(stderr, "*** reset failed ***\n");
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return 0;
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}
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long lsize = CFG_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
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while (1) {
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cache_op(Hit_Writeback_Inv_D, start_addr);
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cache_op(Hit_Invalidate_I, start_addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
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{
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write_32bit_cp0_register(CP0_ENTRYLO0, low0);
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write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
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write_32bit_cp0_register(CP0_ENTRYLO1, low1);
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write_32bit_cp0_register(CP0_ENTRYHI, hi);
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write_32bit_cp0_register(CP0_INDEX, index);
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tlb_write_indexed();
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}
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