mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-31 07:13:44 +09:00
197 lines
6.5 KiB
C
197 lines
6.5 KiB
C
/*
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* Copyright 2005 Freescale Semiconductor.
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* Ed Swarthout (ed.swarthout@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* PEX Configuration space access support for MPC85xx PEX Bridge
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*/
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#include <common.h>
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#include <pci.h>
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#if defined(CONFIG_PCI)
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void
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pci_mpc86xx_init(struct pci_controller *hose)
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{
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volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
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volatile ccsr_pex_t *pex1 = &immap->im_pex1;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
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uint pex1_host = (host1_agent == 2) || (host1_agent == 3);
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u16 reg16, reg16_1, reg16_2, reg16_3;
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u32 reg32, i;
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ulong addr, data;
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uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
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if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
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printf ("PCI-EXPRESS 1: Configured as %s \n",
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pex1_agent ? "Agent" : "Host");
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printf (" Scanning PCI bus");
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debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
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if (pex1->pme_msg_det) {
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pex1->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det);
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}
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debug ("\n");
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}
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hose->first_busno = 0;
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hose->last_busno = 0x7f;
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pci_set_region(hose->regions + 0,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 1,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 2;
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pci_setup_indirect(hose,
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(CFG_IMMR+0x8000),
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(CFG_IMMR+0x8004));
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/*
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* Hose scan.
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*/
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pci_register_hose(hose);
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//#define MPC8548_REV1_PEX12_ERRATA
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#ifdef MPC8548_REV1_PEX12_ERRATA
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/* can only read/write 4 bytes */
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pci_read_config_dword (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®32);
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printf("pex_mpc85xx_init: pex cr %2x %8x\n",PCI_VENDOR_ID, reg32);
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pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®32);
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reg32 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg32);
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#else
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pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®16);
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debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16);
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pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, ®16);
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debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16);
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pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
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pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
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debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16);
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#endif
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/*
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* Clear non-reserved bits in status register.
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*/
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// pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
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// pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
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pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
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pex1->powar1 = 0x8004401c; /* 512M MEM space */
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pex1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
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pex1->potear1 = 0x00000000;
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pex1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
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pex1->powar2 = 0x80088017; /* 16M IO space */
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pex1->potar2 = 0x00000000;
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pex1->potear2 = 0x00000000;
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if (!pex1->piwar1) {
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pex1->pitar1 = 0x00000000;
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pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff;
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pex1->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
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* Snoop R/W, 2G */
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}
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pex1->pitar2 = 0x00000000;
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pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff;
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pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
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/* if (pex1_host) { */
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/* #ifdef MPC8548_REV1_PEX12_ERRATA */
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/* pci_write_config_dword (PCI_BDF(0,0,0), 0x18, 0x00ff0100); */
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/* #else */
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*(u32 *)(0xf8008000)= 0x80000000;
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debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
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pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20);
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pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00);
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pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F);
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/* #endif */
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*(u32 *)(0xf8008000)= 0x80200000;
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debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
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*(u32 *)(0xf8008000)= 0x80200000;
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debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
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*(u32 *)(0xf8008000)= 0x80200000;
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debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
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hose->last_busno = pci_hose_scan(hose);
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hose->last_busno = 0x21;
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debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno);
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debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno);
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printf("....PCI scan & enumeration done\n");
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/* *(u32 *)(0xf8008000)= 0x80000000 | (0x12 << 11); */
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/* printf("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); */
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/* if (hose->last_busno < 1) { */
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/* hose->last_busno=1; /\*Hack*\/ */
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/* } else { */
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/* hose->last_busno = 0; */
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/* } */
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/*}*/
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/* pci_read_config_dword (PCI_BDF(1,0,0), 0x18, ®32); */
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/* printf("pex_mpc86xx_init: pex cr %2x %8x\n",0x18, reg32); */
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}
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#endif /* CONFIG_PCI */
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