mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
![Paul Kocialkowski](/assets/img/avatar_default.png)
Sunxi platforms come with at least 3 TWI (I2C) controllers and some platforms even have up to 5. This adds support for every controller on each supported platform, which is especially useful when using expansion ports on single-board- computers. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
490 lines
14 KiB
C
490 lines
14 KiB
C
/*
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* (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
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* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some board init for the Allwinner A10-evb board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mmc.h>
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#ifdef CONFIG_AXP152_POWER
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#include <axp152.h>
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#endif
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#ifdef CONFIG_AXP209_POWER
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#include <axp209.h>
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#endif
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#ifdef CONFIG_AXP221_POWER
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#include <axp221.h>
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#endif
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/display.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/usbc.h>
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#include <asm/io.h>
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#include <linux/usb/musb.h>
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#include <net.h>
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#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
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/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
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int soft_i2c_gpio_sda;
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int soft_i2c_gpio_scl;
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* add board specific code here */
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int board_init(void)
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{
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int id_pfr1;
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gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
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asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
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debug("id_pfr1: 0x%08x\n", id_pfr1);
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/* Generic Timer Extension available? */
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if ((id_pfr1 >> 16) & 0xf) {
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debug("Setting CNTFRQ\n");
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/* CNTFRQ == 24 MHz */
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asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
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}
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
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return 0;
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}
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#ifdef CONFIG_GENERIC_MMC
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static void mmc_pinmux_setup(int sdc)
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{
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unsigned int pin;
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__maybe_unused int pins;
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switch (sdc) {
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case 0:
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/* SDC0: PF0-PF5 */
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for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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case 1:
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pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
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if (pins == SUNXI_GPIO_H) {
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/* SDC1: PH22-PH-27 */
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for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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} else {
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/* SDC1: PG0-PG5 */
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for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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}
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#elif defined(CONFIG_MACH_SUN5I)
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/* SDC1: PG3-PG8 */
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for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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#elif defined(CONFIG_MACH_SUN6I)
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/* SDC1: PG0-PG5 */
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for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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#elif defined(CONFIG_MACH_SUN8I)
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if (pins == SUNXI_GPIO_D) {
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/* SDC1: PD2-PD7 */
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for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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} else {
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/* SDC1: PG0-PG5 */
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for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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}
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#endif
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break;
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case 2:
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pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
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/* SDC2: PC6-PC11 */
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for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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#elif defined(CONFIG_MACH_SUN5I)
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if (pins == SUNXI_GPIO_E) {
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/* SDC2: PE4-PE9 */
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for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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} else {
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/* SDC2: PC6-PC15 */
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for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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}
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#elif defined(CONFIG_MACH_SUN6I)
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if (pins == SUNXI_GPIO_A) {
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/* SDC2: PA9-PA14 */
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for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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} else {
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/* SDC2: PC6-PC15, PC24 */
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for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
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sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
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}
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#elif defined(CONFIG_MACH_SUN8I)
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/* SDC2: PC5-PC6, PC8-PC16 */
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for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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#endif
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break;
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case 3:
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pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
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/* SDC3: PI4-PI9 */
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for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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#elif defined(CONFIG_MACH_SUN6I)
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if (pins == SUNXI_GPIO_A) {
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/* SDC3: PA9-PA14 */
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for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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} else {
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/* SDC3: PC6-PC15, PC24 */
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for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
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sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
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}
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#endif
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break;
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default:
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printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
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break;
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}
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}
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int board_mmc_init(bd_t *bis)
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{
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__maybe_unused struct mmc *mmc0, *mmc1;
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__maybe_unused char buf[512];
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mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
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mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
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if (!mmc0)
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return -1;
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#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
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mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
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mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
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if (!mmc1)
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return -1;
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#endif
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#if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
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/*
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* Both mmc0 and mmc2 are bootable, figure out where we're booting
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* from. Try mmc0 first, just like the brom does.
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*/
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if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 &&
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mmc0->block_dev.block_read(0, 16, 1, buf) == 1) {
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buf[12] = 0;
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if (strcmp(&buf[4], "eGON.BT0") == 0)
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return 0;
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}
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/* no bootable card in mmc0, so we must be booting from mmc2, swap */
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mmc0->block_dev.dev = 1;
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mmc1->block_dev.dev = 0;
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#endif
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return 0;
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}
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#endif
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void i2c_init_board(void)
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{
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#ifdef CONFIG_I2C0_ENABLE
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
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clock_twi_onoff(0, 1);
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#elif defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
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clock_twi_onoff(0, 1);
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#elif defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
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clock_twi_onoff(0, 1);
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#endif
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#endif
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#ifdef CONFIG_I2C1_ENABLE
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
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clock_twi_onoff(1, 1);
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#elif defined(CONFIG_MACH_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
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clock_twi_onoff(1, 1);
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#elif defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
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clock_twi_onoff(1, 1);
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#elif defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
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clock_twi_onoff(1, 1);
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#endif
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#endif
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#ifdef CONFIG_I2C2_ENABLE
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
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clock_twi_onoff(2, 1);
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#elif defined(CONFIG_MACH_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
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clock_twi_onoff(2, 1);
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#elif defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
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clock_twi_onoff(2, 1);
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#elif defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
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sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
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clock_twi_onoff(2, 1);
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#endif
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#endif
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#ifdef CONFIG_I2C3_ENABLE
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#if defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
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sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
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clock_twi_onoff(3, 1);
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#elif defined(CONFIG_MACH_SUN7I)
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sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
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sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
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clock_twi_onoff(3, 1);
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#endif
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#endif
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#ifdef CONFIG_I2C4_ENABLE
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#if defined(CONFIG_MACH_SUN7I)
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sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
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sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
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clock_twi_onoff(4, 1);
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#endif
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#endif
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#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
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soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
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soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
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#endif
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}
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#ifdef CONFIG_SPL_BUILD
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void sunxi_board_init(void)
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{
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int power_failed = 0;
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unsigned long ramsize;
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#ifdef CONFIG_AXP152_POWER
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power_failed = axp152_init();
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power_failed |= axp152_set_dcdc2(1400);
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power_failed |= axp152_set_dcdc3(1500);
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power_failed |= axp152_set_dcdc4(1250);
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power_failed |= axp152_set_ldo2(3000);
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#endif
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#ifdef CONFIG_AXP209_POWER
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power_failed |= axp209_init();
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power_failed |= axp209_set_dcdc2(1400);
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power_failed |= axp209_set_dcdc3(1250);
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power_failed |= axp209_set_ldo2(3000);
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power_failed |= axp209_set_ldo3(2800);
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power_failed |= axp209_set_ldo4(2800);
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#endif
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#ifdef CONFIG_AXP221_POWER
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power_failed = axp221_init();
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power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT);
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power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */
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power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */
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#ifdef CONFIG_MACH_SUN6I
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power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */
|
|
#else
|
|
power_failed |= axp221_set_dcdc4(0); /* A23:unused */
|
|
#endif
|
|
power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */
|
|
power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
|
|
power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
|
|
power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
|
|
power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
|
|
power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
|
|
power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT);
|
|
#endif
|
|
|
|
printf("DRAM:");
|
|
ramsize = sunxi_dram_init();
|
|
printf(" %lu MiB\n", ramsize >> 20);
|
|
if (!ramsize)
|
|
hang();
|
|
|
|
/*
|
|
* Only clock up the CPU to full speed if we are reasonably
|
|
* assured it's being powered with suitable core voltage
|
|
*/
|
|
if (!power_failed)
|
|
clock_set_pll1(CONFIG_SYS_CLK_FREQ);
|
|
else
|
|
printf("Failed to set core voltage! Can't set CPU frequency\n");
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
|
|
static struct musb_hdrc_config musb_config = {
|
|
.multipoint = 1,
|
|
.dyn_fifo = 1,
|
|
.num_eps = 6,
|
|
.ram_bits = 11,
|
|
};
|
|
|
|
static struct musb_hdrc_platform_data musb_plat = {
|
|
#if defined(CONFIG_MUSB_HOST)
|
|
.mode = MUSB_HOST,
|
|
#else
|
|
.mode = MUSB_PERIPHERAL,
|
|
#endif
|
|
.config = &musb_config,
|
|
.power = 250,
|
|
.platform_ops = &sunxi_musb_ops,
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_GADGET
|
|
int g_dnl_board_usb_cable_connected(void)
|
|
{
|
|
return sunxi_usbc_vbus_detect(0);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_MISC_INIT_R
|
|
int misc_init_r(void)
|
|
{
|
|
char serial_string[17] = { 0 };
|
|
unsigned int sid[4];
|
|
uint8_t mac_addr[6];
|
|
int ret;
|
|
|
|
ret = sunxi_get_sid(sid);
|
|
if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
|
|
if (!getenv("ethaddr")) {
|
|
/* Non OUI / registered MAC address */
|
|
mac_addr[0] = 0x02;
|
|
mac_addr[1] = (sid[0] >> 0) & 0xff;
|
|
mac_addr[2] = (sid[3] >> 24) & 0xff;
|
|
mac_addr[3] = (sid[3] >> 16) & 0xff;
|
|
mac_addr[4] = (sid[3] >> 8) & 0xff;
|
|
mac_addr[5] = (sid[3] >> 0) & 0xff;
|
|
|
|
eth_setenv_enetaddr("ethaddr", mac_addr);
|
|
}
|
|
|
|
if (!getenv("serial#")) {
|
|
snprintf(serial_string, sizeof(serial_string),
|
|
"%08x%08x", sid[0], sid[3]);
|
|
|
|
setenv("serial#", serial_string);
|
|
}
|
|
}
|
|
|
|
#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
|
|
musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
|
|
#endif
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_OF_BOARD_SETUP
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
#ifdef CONFIG_VIDEO_DT_SIMPLEFB
|
|
return sunxi_simplefb_setup(blob);
|
|
#endif
|
|
}
|
|
#endif /* CONFIG_OF_BOARD_SETUP */
|