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![Stephen Warren](/assets/img/avatar_default.png)
In tegra20_slink.c, the set_mode() function may be executed before the
SPI bus is claimed the first time, and hence the clocks to the SPI
controller may not be running. If so, any register read/write at this
time will hang the CPU. Fix this by ensuring the clock is running as soon
as the driver is probed. This is observed on the Tegra30 Beaver board.
Apply the same clock initialization fix to all other Tegra SPI drivers so
that if set_mode() is ever implemented there, the same bug will not appear.
Note that tegra114_spi.c already operates in this fashion.
The clock manipulation code is copied from claim_bus() to probe() rather
than moved. This ensures that any calls to set_speed() take effect; the
clock can't be set once during probe and left unchanged.
Fixes: 5cb1b7b395
("spi: tegra20: Add support for mode selection")
Cc: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
421 lines
12 KiB
C
421 lines
12 KiB
C
/*
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* NVIDIA Tegra210 QSPI controller driver
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*
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* (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <spi.h>
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#include <fdtdec.h>
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#include "tegra_spi.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* COMMAND1 */
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#define QSPI_CMD1_GO BIT(31)
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#define QSPI_CMD1_M_S BIT(30)
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#define QSPI_CMD1_MODE_MASK GENMASK(1,0)
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#define QSPI_CMD1_MODE_SHIFT 28
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#define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0)
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#define QSPI_CMD1_CS_SEL_SHIFT 26
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#define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22)
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#define QSPI_CMD1_CS_SW_HW BIT(21)
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#define QSPI_CMD1_CS_SW_VAL BIT(20)
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#define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0)
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#define QSPI_CMD1_IDLE_SDA_SHIFT 18
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#define QSPI_CMD1_BIDIR BIT(17)
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#define QSPI_CMD1_LSBI_FE BIT(16)
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#define QSPI_CMD1_LSBY_FE BIT(15)
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#define QSPI_CMD1_BOTH_EN_BIT BIT(14)
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#define QSPI_CMD1_BOTH_EN_BYTE BIT(13)
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#define QSPI_CMD1_RX_EN BIT(12)
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#define QSPI_CMD1_TX_EN BIT(11)
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#define QSPI_CMD1_PACKED BIT(5)
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#define QSPI_CMD1_BITLEN_MASK GENMASK(4,0)
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#define QSPI_CMD1_BITLEN_SHIFT 0
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/* COMMAND2 */
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#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
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#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6)
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#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
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#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0)
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/* TRANSFER STATUS */
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#define QSPI_XFER_STS_RDY BIT(30)
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/* FIFO STATUS */
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#define QSPI_FIFO_STS_CS_INACTIVE BIT(31)
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#define QSPI_FIFO_STS_FRAME_END BIT(30)
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#define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
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#define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
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#define QSPI_FIFO_STS_ERR BIT(8)
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#define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7)
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#define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6)
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#define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5)
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#define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4)
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#define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3)
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#define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
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#define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1)
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#define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
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#define QSPI_TIMEOUT 1000
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struct qspi_regs {
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u32 command1; /* 000:QSPI_COMMAND1 register */
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u32 command2; /* 004:QSPI_COMMAND2 register */
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u32 timing1; /* 008:QSPI_CS_TIM1 register */
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u32 timing2; /* 00c:QSPI_CS_TIM2 register */
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u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */
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u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */
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u32 tx_data; /* 018:QSPI_TX_DATA register */
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u32 rx_data; /* 01c:QSPI_RX_DATA register */
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u32 dma_ctl; /* 020:QSPI_DMA_CTL register */
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u32 dma_blk; /* 024:QSPI_DMA_BLK register */
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u32 rsvd[56]; /* 028-107 reserved */
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u32 tx_fifo; /* 108:QSPI_FIFO1 register */
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u32 rsvd2[31]; /* 10c-187 reserved */
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u32 rx_fifo; /* 188:QSPI_FIFO2 register */
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u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */
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};
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struct tegra210_qspi_priv {
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struct qspi_regs *regs;
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unsigned int freq;
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unsigned int mode;
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int periph_id;
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int valid;
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int last_transaction_us;
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};
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static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
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{
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struct tegra_spi_platdata *plat = bus->platdata;
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const void *blob = gd->fdt_blob;
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int node = bus->of_offset;
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plat->base = dev_get_addr(bus);
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plat->periph_id = clock_decode_periph_id(blob, node);
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if (plat->periph_id == PERIPH_ID_NONE) {
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debug("%s: could not decode periph id %d\n", __func__,
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plat->periph_id);
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return -FDT_ERR_NOTFOUND;
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}
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/* Use 500KHz as a suitable default */
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plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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500000);
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plat->deactivate_delay_us = fdtdec_get_int(blob, node,
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"spi-deactivate-delay", 0);
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debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
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__func__, plat->base, plat->periph_id, plat->frequency,
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plat->deactivate_delay_us);
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return 0;
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}
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static int tegra210_qspi_probe(struct udevice *bus)
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{
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struct tegra_spi_platdata *plat = dev_get_platdata(bus);
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struct tegra210_qspi_priv *priv = dev_get_priv(bus);
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priv->regs = (struct qspi_regs *)plat->base;
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priv->last_transaction_us = timer_get_us();
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priv->freq = plat->frequency;
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priv->periph_id = plat->periph_id;
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/* Change SPI clock to correct frequency, PLLP_OUT0 source */
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clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
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return 0;
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}
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static int tegra210_qspi_claim_bus(struct udevice *bus)
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{
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struct tegra210_qspi_priv *priv = dev_get_priv(bus);
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struct qspi_regs *regs = priv->regs;
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/* Change SPI clock to correct frequency, PLLP_OUT0 source */
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clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
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debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status));
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/* Set master mode and sw controlled CS */
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setbits_le32(®s->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW |
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(priv->mode << QSPI_CMD1_MODE_SHIFT));
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debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1));
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return 0;
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}
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/**
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* Activate the CS by driving it LOW
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*
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* @param slave Pointer to spi_slave to which controller has to
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* communicate with
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*/
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static void spi_cs_activate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
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struct tegra210_qspi_priv *priv = dev_get_priv(bus);
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/* If it's too soon to do another transaction, wait */
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if (pdata->deactivate_delay_us &&
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priv->last_transaction_us) {
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ulong delay_us; /* The delay completed so far */
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delay_us = timer_get_us() - priv->last_transaction_us;
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if (delay_us < pdata->deactivate_delay_us)
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udelay(pdata->deactivate_delay_us - delay_us);
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}
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clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
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}
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/**
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* Deactivate the CS by driving it HIGH
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*
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* @param slave Pointer to spi_slave to which controller has to
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* communicate with
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*/
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static void spi_cs_deactivate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
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struct tegra210_qspi_priv *priv = dev_get_priv(bus);
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setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
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/* Remember time of this transaction so we can honour the bus delay */
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if (pdata->deactivate_delay_us)
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priv->last_transaction_us = timer_get_us();
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debug("Deactivate CS, bus '%s'\n", bus->name);
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}
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static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *data_out, void *data_in,
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unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct tegra210_qspi_priv *priv = dev_get_priv(bus);
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struct qspi_regs *regs = priv->regs;
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u32 reg, tmpdout, tmpdin = 0;
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const u8 *dout = data_out;
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u8 *din = data_in;
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int num_bytes, tm, ret;
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debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
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__func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
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if (bitlen % 8)
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return -1;
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num_bytes = bitlen / 8;
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ret = 0;
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/* clear all error status bits */
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reg = readl(®s->fifo_status);
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writel(reg, ®s->fifo_status);
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/* flush RX/TX FIFOs */
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setbits_le32(®s->fifo_status,
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(QSPI_FIFO_STS_RX_FIFO_FLUSH |
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QSPI_FIFO_STS_TX_FIFO_FLUSH));
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tm = QSPI_TIMEOUT;
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while ((tm && readl(®s->fifo_status) &
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(QSPI_FIFO_STS_RX_FIFO_FLUSH |
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QSPI_FIFO_STS_TX_FIFO_FLUSH))) {
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tm--;
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udelay(1);
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}
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if (!tm) {
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printf("%s: timeout during QSPI FIFO flush!\n",
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__func__);
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return -1;
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}
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/*
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* Notes:
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* 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs;
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* 2. don't set RX_EN and TX_EN yet.
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* (SW needs to make sure that while programming the blk_size,
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* tx_en and rx_en bits must be zero)
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* [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set
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* i.e., both dout and din are not NULL.
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*/
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clrsetbits_le32(®s->command1,
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(QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE |
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QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN),
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(spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT));
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/* set xfer size to 1 block (32 bits) */
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writel(0, ®s->dma_blk);
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(dev);
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/* handle data in 32-bit chunks */
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while (num_bytes > 0) {
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int bytes;
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tmpdout = 0;
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bytes = (num_bytes > 4) ? 4 : num_bytes;
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if (dout != NULL) {
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memcpy((void *)&tmpdout, (void *)dout, bytes);
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dout += bytes;
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num_bytes -= bytes;
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writel(tmpdout, ®s->tx_fifo);
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setbits_le32(®s->command1, QSPI_CMD1_TX_EN);
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}
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if (din != NULL)
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setbits_le32(®s->command1, QSPI_CMD1_RX_EN);
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/* clear ready bit */
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setbits_le32(®s->xfer_status, QSPI_XFER_STS_RDY);
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clrsetbits_le32(®s->command1,
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QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT,
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(bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT);
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/* Need to stabilize other reg bits before GO bit set.
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* As per the TRM:
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* "For successful operation at various freq combinations,
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* a minimum of 4-5 spi_clk cycle delay might be required
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* before enabling the PIO or DMA bits. The worst case delay
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* calculation can be done considering slowest qspi_clk as
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* 1MHz. Based on that 1us delay should be enough before
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* enabling PIO or DMA." Padded another 1us for safety.
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*/
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udelay(2);
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setbits_le32(®s->command1, QSPI_CMD1_GO);
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udelay(1);
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/*
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* Wait for SPI transmit FIFO to empty, or to time out.
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* The RX FIFO status will be read and cleared last
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*/
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for (tm = 0; tm < QSPI_TIMEOUT; ++tm) {
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u32 fifo_status, xfer_status;
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xfer_status = readl(®s->xfer_status);
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if (!(xfer_status & QSPI_XFER_STS_RDY))
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continue;
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fifo_status = readl(®s->fifo_status);
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if (fifo_status & QSPI_FIFO_STS_ERR) {
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debug("%s: got a fifo error: ", __func__);
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if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF)
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debug("tx FIFO overflow ");
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if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR)
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debug("tx FIFO underrun ");
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if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF)
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debug("rx FIFO overflow ");
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if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR)
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debug("rx FIFO underrun ");
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if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL)
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debug("tx FIFO full ");
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if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY)
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debug("tx FIFO empty ");
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if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL)
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debug("rx FIFO full ");
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if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)
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debug("rx FIFO empty ");
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debug("\n");
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break;
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}
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if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) {
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tmpdin = readl(®s->rx_fifo);
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if (din != NULL) {
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memcpy(din, &tmpdin, bytes);
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din += bytes;
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num_bytes -= bytes;
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}
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}
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break;
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}
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if (tm >= QSPI_TIMEOUT)
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ret = tm;
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/* clear ACK RDY, etc. bits */
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writel(readl(®s->fifo_status), ®s->fifo_status);
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(dev);
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debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
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__func__, tmpdin, readl(®s->fifo_status));
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if (ret) {
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printf("%s: timeout during SPI transfer, tm %d\n",
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__func__, ret);
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return -1;
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}
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return ret;
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}
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static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
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{
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struct tegra_spi_platdata *plat = bus->platdata;
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struct tegra210_qspi_priv *priv = dev_get_priv(bus);
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if (speed > plat->frequency)
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speed = plat->frequency;
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priv->freq = speed;
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debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
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return 0;
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}
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static int tegra210_qspi_set_mode(struct udevice *bus, uint mode)
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{
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struct tegra210_qspi_priv *priv = dev_get_priv(bus);
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priv->mode = mode;
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debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
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return 0;
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}
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static const struct dm_spi_ops tegra210_qspi_ops = {
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.claim_bus = tegra210_qspi_claim_bus,
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.xfer = tegra210_qspi_xfer,
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.set_speed = tegra210_qspi_set_speed,
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.set_mode = tegra210_qspi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct udevice_id tegra210_qspi_ids[] = {
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{ .compatible = "nvidia,tegra210-qspi" },
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{ }
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};
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U_BOOT_DRIVER(tegra210_qspi) = {
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.name = "tegra210-qspi",
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.id = UCLASS_SPI,
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.of_match = tegra210_qspi_ids,
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.ops = &tegra210_qspi_ops,
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.ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv),
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.per_child_auto_alloc_size = sizeof(struct spi_slave),
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.probe = tegra210_qspi_probe,
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};
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