mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 08:58:52 +09:00
![Lokesh Vutla](/assets/img/avatar_default.png)
Sync the k3-am654 specific dts files from Linux next with tag 20181019. This changes are in queue for Linux v4.20-rc1 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
98 lines
2.9 KiB
Plaintext
98 lines
2.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Device Tree Source for AM6 SoC Family
|
|
*
|
|
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/ {
|
|
model = "Texas Instruments K3 AM654 SoC";
|
|
compatible = "ti,am654";
|
|
interrupt-parent = <&gic500>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
aliases {
|
|
serial0 = &wkup_uart0;
|
|
serial1 = &mcu_uart0;
|
|
serial2 = &main_uart0;
|
|
serial3 = &main_uart1;
|
|
serial4 = &main_uart2;
|
|
};
|
|
|
|
chosen { };
|
|
|
|
firmware {
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
|
|
psci: psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
};
|
|
|
|
a53_timer0: timer-cl0-cpu0 {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
|
};
|
|
|
|
pmu: pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
/* Recommendation from GIC500 TRM Table A.3 */
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
cbass_main: interconnect@100000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
|
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
|
|
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
|
|
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
|
|
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
|
|
/* MCUSS Range */
|
|
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
|
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
|
|
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
|
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
|
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
|
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
|
|
|
|
cbass_mcu: interconnect@28380000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
|
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
|
|
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
|
|
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
|
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
|
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
|
|
|
|
cbass_wakeup: interconnect@42040000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
/* WKUP Basic peripherals */
|
|
ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
/* Now include the peripherals for each bus segments */
|
|
#include "k3-am65-main.dtsi"
|
|
#include "k3-am65-mcu.dtsi"
|
|
#include "k3-am65-wakeup.dtsi"
|