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![Suneel Garapati](/assets/img/avatar_default.png)
Adds support for Network Interface controllers found on OcteonTX SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
509 lines
12 KiB
C
509 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#ifndef NIC_H
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#define NIC_H
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#include <linux/netdevice.h>
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#include "bgx.h"
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#define PCI_DEVICE_ID_CAVIUM_NICVF_1 0x0011
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/* Subsystem device IDs */
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#define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E
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#define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E
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#define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E
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#define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E
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#define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134
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#define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234
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#define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334
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#define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */
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#define NIC_CHANS_PER_INF 128
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#define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF)
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/* PCI BAR nos */
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#define PCI_CFG_REG_BAR_NUM 0
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#define PCI_MSIX_REG_BAR_NUM 4
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/* NIC SRIOV VF count */
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#define MAX_NUM_VFS_SUPPORTED 128
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#define DEFAULT_NUM_VF_ENABLED 8
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#define NIC_TNS_BYPASS_MODE 0
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#define NIC_TNS_MODE 1
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/* NIC priv flags */
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#define NIC_SRIOV_ENABLED BIT(0)
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#define NIC_TNS_ENABLED BIT(1)
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/* VNIC HW optimiation features */
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#define VNIC_RX_CSUM_OFFLOAD_SUPPORT
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#undef VNIC_TX_CSUM_OFFLOAD_SUPPORT
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#undef VNIC_SG_SUPPORT
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#undef VNIC_TSO_SUPPORT
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#undef VNIC_LRO_SUPPORT
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#undef VNIC_RSS_SUPPORT
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/* TSO not supported in Thunder pass1 */
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#ifdef VNIC_TSO_SUPPORT
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#define VNIC_SW_TSO_SUPPORT
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#undef VNIC_HW_TSO_SUPPORT
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#endif
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/* ETHTOOL enable or disable, undef this to disable */
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#define NICVF_ETHTOOL_ENABLE
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/* Min/Max packet size */
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#define NIC_HW_MIN_FRS 64
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#define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */
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/* Max pkinds */
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#define NIC_MAX_PKIND 16
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/* Max when CPI_ALG is IP diffserv */
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#define NIC_MAX_CPI_PER_LMAC 64
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/* NIC VF Interrupts */
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#define NICVF_INTR_CQ 0
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#define NICVF_INTR_SQ 1
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#define NICVF_INTR_RBDR 2
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#define NICVF_INTR_PKT_DROP 3
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#define NICVF_INTR_TCP_TIMER 4
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#define NICVF_INTR_MBOX 5
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#define NICVF_INTR_QS_ERR 6
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#define NICVF_INTR_CQ_SHIFT 0
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#define NICVF_INTR_SQ_SHIFT 8
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#define NICVF_INTR_RBDR_SHIFT 16
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#define NICVF_INTR_PKT_DROP_SHIFT 20
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#define NICVF_INTR_TCP_TIMER_SHIFT 21
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#define NICVF_INTR_MBOX_SHIFT 22
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#define NICVF_INTR_QS_ERR_SHIFT 23
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#define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
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#define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
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#define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
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#define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT)
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#define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT)
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#define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT)
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#define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT)
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/* MSI-X interrupts */
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#define NIC_PF_MSIX_VECTORS 10
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#define NIC_VF_MSIX_VECTORS 20
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#define NIC_PF_INTR_ID_ECC0_SBE 0
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#define NIC_PF_INTR_ID_ECC0_DBE 1
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#define NIC_PF_INTR_ID_ECC1_SBE 2
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#define NIC_PF_INTR_ID_ECC1_DBE 3
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#define NIC_PF_INTR_ID_ECC2_SBE 4
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#define NIC_PF_INTR_ID_ECC2_DBE 5
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#define NIC_PF_INTR_ID_ECC3_SBE 6
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#define NIC_PF_INTR_ID_ECC3_DBE 7
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#define NIC_PF_INTR_ID_MBOX0 8
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#define NIC_PF_INTR_ID_MBOX1 9
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/* Global timer for CQ timer thresh interrupts
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* Calculated for SCLK of 700Mhz
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* value written should be a 1/16thof what is expected
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*
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* 1 tick per ms
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*/
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#define NICPF_CLK_PER_INT_TICK 43750
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struct nicvf_cq_poll {
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u8 cq_idx; /* Completion queue index */
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};
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#define NIC_MAX_RSS_HASH_BITS 8
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#define NIC_MAX_RSS_IDR_TBL_SIZE BIT(NIC_MAX_RSS_HASH_BITS)
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#define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
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#ifdef VNIC_RSS_SUPPORT
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struct nicvf_rss_info {
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bool enable;
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#define RSS_L2_EXTENDED_HASH_ENA BIT(0)
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#define RSS_IP_HASH_ENA BIT(1)
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#define RSS_TCP_HASH_ENA BIT(2)
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#define RSS_TCP_SYN_DIS BIT(3)
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#define RSS_UDP_HASH_ENA BIT(4)
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#define RSS_L4_EXTENDED_HASH_ENA BIT(5)
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#define RSS_ROCE_ENA BIT(6)
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#define RSS_L3_BI_DIRECTION_ENA BIT(7)
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#define RSS_L4_BI_DIRECTION_ENA BIT(8)
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u64 cfg;
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u8 hash_bits;
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u16 rss_size;
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u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
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u64 key[RSS_HASH_KEY_SIZE];
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};
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#endif
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enum rx_stats_reg_offset {
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RX_OCTS = 0x0,
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RX_UCAST = 0x1,
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RX_BCAST = 0x2,
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RX_MCAST = 0x3,
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RX_RED = 0x4,
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RX_RED_OCTS = 0x5,
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RX_ORUN = 0x6,
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RX_ORUN_OCTS = 0x7,
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RX_FCS = 0x8,
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RX_L2ERR = 0x9,
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RX_DRP_BCAST = 0xa,
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RX_DRP_MCAST = 0xb,
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RX_DRP_L3BCAST = 0xc,
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RX_DRP_L3MCAST = 0xd,
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RX_STATS_ENUM_LAST,
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};
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enum tx_stats_reg_offset {
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TX_OCTS = 0x0,
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TX_UCAST = 0x1,
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TX_BCAST = 0x2,
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TX_MCAST = 0x3,
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TX_DROP = 0x4,
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TX_STATS_ENUM_LAST,
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};
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struct nicvf_hw_stats {
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u64 rx_bytes_ok;
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u64 rx_ucast_frames_ok;
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u64 rx_bcast_frames_ok;
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u64 rx_mcast_frames_ok;
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u64 rx_fcs_errors;
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u64 rx_l2_errors;
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u64 rx_drop_red;
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u64 rx_drop_red_bytes;
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u64 rx_drop_overrun;
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u64 rx_drop_overrun_bytes;
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u64 rx_drop_bcast;
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u64 rx_drop_mcast;
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u64 rx_drop_l3_bcast;
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u64 rx_drop_l3_mcast;
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u64 tx_bytes_ok;
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u64 tx_ucast_frames_ok;
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u64 tx_bcast_frames_ok;
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u64 tx_mcast_frames_ok;
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u64 tx_drops;
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};
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struct nicvf_drv_stats {
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/* Rx */
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u64 rx_frames_ok;
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u64 rx_frames_64;
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u64 rx_frames_127;
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u64 rx_frames_255;
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u64 rx_frames_511;
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u64 rx_frames_1023;
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u64 rx_frames_1518;
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u64 rx_frames_jumbo;
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u64 rx_drops;
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/* Tx */
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u64 tx_frames_ok;
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u64 tx_drops;
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u64 tx_busy;
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u64 tx_tso;
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};
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struct hw_info {
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u8 bgx_cnt;
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u8 chans_per_lmac;
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u8 chans_per_bgx; /* Rx/Tx chans */
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u8 chans_per_rgx;
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u8 chans_per_lbk;
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u16 cpi_cnt;
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u16 rssi_cnt;
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u16 rss_ind_tbl_size;
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u16 tl4_cnt;
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u16 tl3_cnt;
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u8 tl2_cnt;
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u8 tl1_cnt;
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bool tl1_per_bgx; /* TL1 per BGX or per LMAC */
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u8 model_id;
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};
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struct nicvf {
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struct udevice *dev;
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u8 vf_id;
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bool sqs_mode:1;
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bool loopback_supported:1;
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u8 tns_mode;
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u8 node;
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u16 mtu;
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struct queue_set *qs;
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#define MAX_SQS_PER_VF_SINGLE_NODE 5
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#define MAX_SQS_PER_VF 11
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u8 num_qs;
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void *addnl_qs;
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u16 vf_mtu;
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void __iomem *reg_base;
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#define MAX_QUEUES_PER_QSET 8
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struct nicvf_cq_poll *napi[8];
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u8 cpi_alg;
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struct nicvf_hw_stats stats;
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struct nicvf_drv_stats drv_stats;
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struct nicpf *nicpf;
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/* VF <-> PF mailbox communication */
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bool pf_acked;
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bool pf_nacked;
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bool set_mac_pending;
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bool link_up;
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u8 duplex;
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u32 speed;
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u8 rev_id;
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u8 rx_queues;
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u8 tx_queues;
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bool open;
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bool rb_alloc_fail;
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void *rcv_buf;
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bool hw_tso;
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};
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static inline int node_id(void *addr)
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{
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return ((uintptr_t)addr >> 44) & 0x3;
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}
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struct nicpf {
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struct udevice *udev;
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struct hw_info *hw;
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u8 node;
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unsigned int flags;
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u16 total_vf_cnt; /* Total num of VF supported */
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u16 num_vf_en; /* No of VF enabled */
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void __iomem *reg_base; /* Register start address */
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u16 rss_ind_tbl_size;
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u8 num_sqs_en; /* Secondary qsets enabled */
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u64 nicvf[MAX_NUM_VFS_SUPPORTED];
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u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF];
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u8 pqs_vf[MAX_NUM_VFS_SUPPORTED];
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bool sqs_used[MAX_NUM_VFS_SUPPORTED];
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struct pkind_cfg pkind;
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u8 bgx_cnt;
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u8 rev_id;
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#define NIC_SET_VF_LMAC_MAP(bgx, lmac) ((((bgx) & 0xF) << 4) | ((lmac) & 0xF))
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#define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) (((map) >> 4) & 0xF)
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#define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) ((map) & 0xF)
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u8 vf_lmac_map[MAX_LMAC];
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u16 cpi_base[MAX_NUM_VFS_SUPPORTED];
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u64 mac[MAX_NUM_VFS_SUPPORTED];
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bool mbx_lock[MAX_NUM_VFS_SUPPORTED];
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u8 link[MAX_LMAC];
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u8 duplex[MAX_LMAC];
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u32 speed[MAX_LMAC];
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bool vf_enabled[MAX_NUM_VFS_SUPPORTED];
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u16 rssi_base[MAX_NUM_VFS_SUPPORTED];
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u8 lmac_cnt;
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};
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/* PF <--> VF Mailbox communication
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* Eight 64bit registers are shared between PF and VF.
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* Separate set for each VF.
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* Writing '1' into last register mbx7 means end of message.
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*/
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/* PF <--> VF mailbox communication */
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#define NIC_PF_VF_MAILBOX_SIZE 2
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#define NIC_PF_VF_MBX_TIMEOUT 2000 /* ms */
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/* Mailbox message types */
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#define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */
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#define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */
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#define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */
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#define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */
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#define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */
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#define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */
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#define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */
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#define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */
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#define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */
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#define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */
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#define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */
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#define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */
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#define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */
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#define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */
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#define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */
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#define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */
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#define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */
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#define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */
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#define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */
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#define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */
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#define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */
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#define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */
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#define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */
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#define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */
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struct nic_cfg_msg {
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u8 msg;
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u8 vf_id;
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u8 node_id;
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bool tns_mode:1;
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bool sqs_mode:1;
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bool loopback_supported:1;
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u8 mac_addr[6];
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};
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/* Qset configuration */
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struct qs_cfg_msg {
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u8 msg;
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u8 num;
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u8 sqs_count;
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u64 cfg;
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};
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/* Receive queue configuration */
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struct rq_cfg_msg {
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u8 msg;
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u8 qs_num;
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u8 rq_num;
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u64 cfg;
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};
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/* Send queue configuration */
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struct sq_cfg_msg {
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u8 msg;
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u8 qs_num;
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u8 sq_num;
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bool sqs_mode;
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u64 cfg;
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};
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/* Set VF's MAC address */
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struct set_mac_msg {
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u8 msg;
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u8 vf_id;
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u8 mac_addr[6];
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};
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/* Set Maximum frame size */
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struct set_frs_msg {
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u8 msg;
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u8 vf_id;
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u16 max_frs;
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};
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/* Set CPI algorithm type */
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struct cpi_cfg_msg {
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u8 msg;
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u8 vf_id;
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u8 rq_cnt;
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u8 cpi_alg;
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};
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/* Get RSS table size */
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struct rss_sz_msg {
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u8 msg;
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u8 vf_id;
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u16 ind_tbl_size;
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};
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/* Set RSS configuration */
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struct rss_cfg_msg {
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u8 msg;
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u8 vf_id;
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u8 hash_bits;
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u8 tbl_len;
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u8 tbl_offset;
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#define RSS_IND_TBL_LEN_PER_MBX_MSG 8
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u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG];
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};
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struct bgx_stats_msg {
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u8 msg;
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u8 vf_id;
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u8 rx;
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u8 idx;
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u64 stats;
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};
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/* Physical interface link status */
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struct bgx_link_status {
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u8 msg;
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u8 link_up;
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u8 duplex;
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u32 speed;
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};
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#ifdef VNIC_MULTI_QSET_SUPPORT
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/* Get Extra Qset IDs */
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struct sqs_alloc {
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u8 msg;
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u8 vf_id;
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u8 qs_count;
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};
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struct nicvf_ptr {
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u8 msg;
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u8 vf_id;
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bool sqs_mode;
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u8 sqs_id;
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u64 nicvf;
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};
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#endif
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/* Set interface in loopback mode */
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struct set_loopback {
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u8 msg;
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u8 vf_id;
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bool enable;
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};
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/* 128 bit shared memory between PF and each VF */
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union nic_mbx {
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struct { u8 msg; } msg;
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struct nic_cfg_msg nic_cfg;
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struct qs_cfg_msg qs;
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struct rq_cfg_msg rq;
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struct sq_cfg_msg sq;
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struct set_mac_msg mac;
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struct set_frs_msg frs;
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struct cpi_cfg_msg cpi_cfg;
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struct rss_sz_msg rss_size;
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struct rss_cfg_msg rss_cfg;
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struct bgx_stats_msg bgx_stats;
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struct bgx_link_status link_status;
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#ifdef VNIC_MULTI_QSET_SUPPORT
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struct sqs_alloc sqs_alloc;
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struct nicvf_ptr nicvf;
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#endif
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struct set_loopback lbk;
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};
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int nicvf_set_real_num_queues(struct udevice *dev,
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int tx_queues, int rx_queues);
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int nicvf_open(struct udevice *dev);
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void nicvf_stop(struct udevice *dev);
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int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx);
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void nicvf_update_stats(struct nicvf *nic);
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|
|
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void nic_handle_mbx_intr(struct nicpf *nic, int vf);
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|
|
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int bgx_poll_for_link(int node, int bgx_idx, int lmacid);
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const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid);
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void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac);
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void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable);
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void bgx_lmac_internal_loopback(int node, int bgx_idx,
|
|
int lmac_idx, bool enable);
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|
|
|
static inline bool pass1_silicon(unsigned int revision, int model_id)
|
|
{
|
|
return ((revision < 8) && (model_id == 0x88));
|
|
}
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|
|
|
static inline bool pass2_silicon(unsigned int revision, int model_id)
|
|
{
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return ((revision >= 8) && (model_id == 0x88));
|
|
}
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|
|
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#endif /* NIC_H */
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