mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 23:48:52 +09:00
![wdenk](/assets/img/avatar_default.png)
1: - board/altera/common/flash.c:flash_erase(): o allow interrupts befor get_timer() call o check-up each erased sector and avoid unexpected timeouts - board/altera/dk1c20/dk1s10.c:board_early_init_f(): o enclose sevenseg_set() in cpp condition - remove the ASMI configuration for DK1S10_standard_32 (never present) - fix some typed in mistakes in the NIOS documentation 2: - split DK1C20 configuration into several header files: o two new files for each NIOS CPU description o U-Boot related part is remaining in DK1C20.h 3: - split DK1S10 configuration into several header files: o two new files for each NIOS CPU description o U-Boot related part is remaining in DK1S10.h 4: - Add support for the Microtronix Linux Development Kit NIOS CPU configuration at the Altera Nios Development Kit, Stratix Edition (DK-1S10) 5: - Add documentation for the Altera Nios Development Kit, Stratix Edition (DK-1S10) 6: - Add support for the Nios Serial Peripharel Interface (SPI) (master only) 7: - Add support for the common U-Boot SPI framework at RTC driver DS1306
243 lines
9.5 KiB
Plaintext
243 lines
9.5 KiB
Plaintext
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===============================================================================
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C P U , M E M O R Y , I N / O U T C O M P O N E N T S
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===============================================================================
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see also [1]-[4]
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CPU: "standard_32"
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32 bit NIOS for 33.333 MHz (nasys_clock_freq = 33333000)
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256 Byte for register file (15 levels)
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no instruction cache
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no data cache
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1 KByte On Chip ROM with GERMS boot monitor
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no On Chip RAM
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MSTEP multiplier
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no Debug Core
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no On Chip Instrumentation (OCI) enabled
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U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
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CFG_NIOS_CPU_ICACHE = 0
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CFG_NIOS_CPU_DCACHE = 0
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CFG_NIOS_CPU_REG_NUMS = 256
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CFG_NIOS_CPU_MUL = 0
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CFG_NIOS_CPU_MSTEP = 1
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CFG_NIOS_CPU_DBG_CORE = 0
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IRQ: Nr. | used by
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------+--------------------------------------------------------
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25 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 25
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26 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 26
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27 | PIO2 | CFG_NIOS_CPU_PIO2_IRQ = 27
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28 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 28 (debug)
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MEMORY: 1 MByte Flash
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256 KByte SRAM
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(SDRAM with standard SODIMM only)
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Timer: TIMER0: high priority programmable timer (IRQ25)
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U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0
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PIO: Nr. | description
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------+--------------------------------------------------------
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PIO0 | SEVENSEG: 16 outputs for user seven segment display
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PIO1 | LED: 8 outputs for user LEDs
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PIO2 | BUTTON: 4 inputs for user push buttons (IRQ27)
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PIO3 | LCD: 11 in/outputs for ASCII LCD
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U-Boot CFG: CFG_NIOS_CPU_SEVENSEG_PIO = 0
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CFG_NIOS_CPU_LED_PIO = 1
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CFG_NIOS_CPU_BUTTON_PIO = 2
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CFG_NIOS_CPU_LCD_PIO = 3
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UART: UART0: fixed baudrate of 115200, fixed protocol 8N2,
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without handshake RTS/CTS (IRQ26)
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UART1: fixed baudrate of 115200, fixed protocol 8N1,
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without handshake RTS/CTS (IRQ28)
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===============================================================================
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M E M O R Y M A P
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===============================================================================
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- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -
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0x00200000 ---15------------8|7-------------0-
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| sector 18 | \
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+ 0x0f0000 |- - - - - - - - - - - - - - - -| |
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| : | |
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Flash |- - - - : - - - -| |
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| sector 5 : | |
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+ 0x020000 |- - - - - - - - -| |
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| sector 4 (size = 0x10000) | |
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+ 0x010000 |- - - - - - - - - - - - - - - -| > CFG_NIOS_CPU_FLASH_SIZE
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| sector 3 (size = 0x08000) | | = 0x00100000
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+ 0x008000 |- - - - - - - - - - - - - - - -| |
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| sector 2 (size = 0x02000) | |
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+ 0x006000 |- - - - - - - - - - - - - - - -| |
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| sector 1 (size = 0x02000) | |
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+ 0x004000 |- - - - - - - - - - - - - - - -| |
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| sector 0 (size = 0x04000) | /
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0x00100000 ---15------------8|7-------------0- CFG_NIOS_CPU_FLASH_BASE
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: gap :
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0x00080000 ---32-----------16|15------------0-
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0x00080000 --+32-----------16|15------------0+
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| . | \ \
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| . | | |
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| . | | > CFG_NIOS_CPU_VEC_SIZE
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| . | | | = 0x00000100
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| . | | /
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0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
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0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK
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| . | | \
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| . | | |
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| . | | > stack area
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| . | | |
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| . | | V
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| . | |
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SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE
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| . | | = 0x00040000
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0x00040000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
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: gap :
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: :
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- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
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: :
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: gap :
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0x00000400 ---32-----------16|15------------0-
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| (unused) | \
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+ 0x1c |- - - - - - - - - - - - - - - -| |
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| (unused) | |
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+ 0x18 |- - - - - - - - - - - - - - - -| |
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| (unused) | |
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+ 0x14 |- - - - - - - - - - - - - - - -| |
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UART1 | (unused) | > 0x00000020
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[2] + 0x10 |- - - - - - - - - - - - - - - -| |
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| control (10 bit) (rw) | |
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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| status (10 bit) (rw) | |
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+ 0x08 |- - - - - - - - - - - - - - - -| |
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| txdata (8 bit) (wo) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| rxdata (8 bit) (ro) | /
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0x000004c0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1
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: gap :
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0x00000490 ---32-----------16|15------------0-
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| (unused) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO3 | (unused) | |
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[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| direction (11 bit) (rw) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (11 bit) (rw) | /
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0x00000480 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
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| edgecapture (12 bit) (rw) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO2 | interruptmask (12 bit) (rw) | |
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[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (12 bit) (ro) | /
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0x00000470 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
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| (unused) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO1 | (unused) | |
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[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| direction (2 bit) (rw) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (2 bit) (rw) | /
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0x00000460 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
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| (unused) | \
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+ 0x1c |- - - - - - - - - - - - - - - -| |
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| (unused) | |
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+ 0x18 |- - - - - - - - - - - - - - - -| |
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| snaph (16 bit) (rw) | |
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+ 0x14 |- - - - - - - - - - - - - - - -| |
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TIMER0 | snapl (16 bit) (rw) | |
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[3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
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| periodh (16 bit) (rw) | |
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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| periodl (16 bit) (rw) | |
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+ 0x08 |- - - - - - - - - - - - - - - -| |
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| control (4 bit) (rw) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| status (2 bit) (rw) | /
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0x00000440 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
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| (unused) | \
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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PIO0 | (unused) | |
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[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
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| (unused) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| data (16 bit) (wo) | /
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0x00000420 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
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| (unused) | \
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+ 0x1c |- - - - - - - - - - - - - - - -| |
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| (unused) | |
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+ 0x18 |- - - - - - - - - - - - - - - -| |
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| (unused) | |
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+ 0x14 |- - - - - - - - - - - - - - - -| |
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UART0 | (unused) | > 0x00000020
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[2] + 0x10 |- - - - - - - - - - - - - - - -| |
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| control (10 bit) (rw) | |
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+ 0x0c |- - - - - - - - - - - - - - - -| |
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| status (10 bit) (rw) | |
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+ 0x08 |- - - - - - - - - - - - - - - -| |
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| txdata (8 bit) (wo) | |
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+ 0x04 |- - - - - - - - - - - - - - - -| |
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| rxdata (8 bit) (ro) | /
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0x00000400 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
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- - - - - - - - - - - on chip memory - - - - - - - - - - -
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0x00000400 ---32-----------16|15------------0-
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GERMS | : | > na_boot_monitor_rom_size
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| : | | = 0x00000400
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| : | /
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0x00000000 |- - - - - - - - - - - - - - - -+- - nasys_reset_address
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0x00000000 ---32-----------16|15------------0- na_boot_monitor_rom
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===============================================================================
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F L A S H M E M O R Y A L L O C A T I O N
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===============================================================================
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0x00200000 ---15------------8|7-------------0-
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| : | \
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SAFE | : | > 256 KByte
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FPGA conf. | : | / (NOT usable by software)
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0x001c0000 --+- - - - - - - -:- - - - - - - -+-
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| : | \
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USER | : | > 256 KByte
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FPGA conf. | : | / (NOT usable by software)
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0x00180000 --+- - - - - - - -:- - - - - - - -+-
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| : | \
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| : | > 512 KByte free for use
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0x00140000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
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0x00100000 ---15------------8|7-------------0-
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===============================================================================
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R E F E R E N C E S
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===============================================================================
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[1] http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf
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[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
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[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
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[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
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===============================================================================
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Stephan Linz <linz@li-pro.net>
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