mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-04 01:03:45 +09:00
f1df936445
This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: Stefan Roese <sr@denx.de>
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_LOGGING_CONFIG_H
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#define _DDR3_LOGGING_CONFIG_H
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#ifdef SILENT_LIB
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#define DEBUG_TRAINING_BIST_ENGINE(level, s)
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#define DEBUG_TRAINING_IP(level, s)
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#define DEBUG_CENTRALIZATION_ENGINE(level, s)
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#define DEBUG_TRAINING_HW_ALG(level, s)
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#define DEBUG_TRAINING_IP_ENGINE(level, s)
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#define DEBUG_LEVELING(level, s)
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#define DEBUG_PBS_ENGINE(level, s)
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#define DEBUG_TRAINING_STATIC_IP(level, s)
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#define DEBUG_TRAINING_ACCESS(level, s)
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#else
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#ifdef LIB_FUNCTIONAL_DEBUG_ONLY
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#define DEBUG_TRAINING_BIST_ENGINE(level, s)
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#define DEBUG_TRAINING_IP_ENGINE(level, s)
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#define DEBUG_TRAINING_IP(level, s) \
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if (level >= debug_training) \
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printf s
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#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
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if (level >= debug_centralization) \
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printf s
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#define DEBUG_TRAINING_HW_ALG(level, s) \
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if (level >= debug_training_hw_alg) \
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printf s
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#define DEBUG_LEVELING(level, s) \
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if (level >= debug_leveling) \
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printf s
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#define DEBUG_PBS_ENGINE(level, s) \
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if (level >= debug_pbs) \
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printf s
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#define DEBUG_TRAINING_STATIC_IP(level, s) \
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if (level >= debug_training_static) \
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printf s
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#define DEBUG_TRAINING_ACCESS(level, s) \
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if (level >= debug_training_access) \
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printf s
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#else
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#define DEBUG_TRAINING_BIST_ENGINE(level, s) \
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if (level >= debug_training_bist) \
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printf s
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#define DEBUG_TRAINING_IP_ENGINE(level, s) \
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if (level >= debug_training_ip) \
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printf s
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#define DEBUG_TRAINING_IP(level, s) \
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if (level >= debug_training) \
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printf s
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#define DEBUG_CENTRALIZATION_ENGINE(level, s) \
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if (level >= debug_centralization) \
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printf s
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#define DEBUG_TRAINING_HW_ALG(level, s) \
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if (level >= debug_training_hw_alg) \
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printf s
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#define DEBUG_LEVELING(level, s) \
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if (level >= debug_leveling) \
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printf s
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#define DEBUG_PBS_ENGINE(level, s) \
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if (level >= debug_pbs) \
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printf s
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#define DEBUG_TRAINING_STATIC_IP(level, s) \
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if (level >= debug_training_static) \
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printf s
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#define DEBUG_TRAINING_ACCESS(level, s) \
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if (level >= debug_training_access) \
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printf s
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#endif
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#endif
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/* Logging defines */
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#define DEBUG_LEVEL_TRACE 1
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#define DEBUG_LEVEL_INFO 2
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#define DEBUG_LEVEL_ERROR 3
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enum ddr_lib_debug_block {
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DEBUG_BLOCK_STATIC,
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DEBUG_BLOCK_TRAINING_MAIN,
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DEBUG_BLOCK_LEVELING,
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DEBUG_BLOCK_CENTRALIZATION,
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DEBUG_BLOCK_PBS,
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DEBUG_BLOCK_IP,
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DEBUG_BLOCK_BIST,
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DEBUG_BLOCK_ALG,
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DEBUG_BLOCK_DEVICE,
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DEBUG_BLOCK_ACCESS,
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DEBUG_STAGES_REG_DUMP,
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/* All excluding IP and REG_DUMP, should be enabled separatelly */
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DEBUG_BLOCK_ALL
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};
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int ddr3_tip_print_log(u32 dev_num, u32 mem_addr);
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int ddr3_tip_print_stability_log(u32 dev_num);
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#endif /* _DDR3_LOGGING_CONFIG_H */
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