173 lines
3.5 KiB
C
173 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*
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* Misc driver for manipulating System control registers
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*/
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#include <dm.h>
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#include <misc.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <dm/device_compat.h>
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#include <mach/mt7620-sysc.h>
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#include "mt7620.h"
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struct mt7620_sysc_priv {
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void __iomem *base;
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};
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static int mt7620_sysc_read(struct udevice *dev, int offset, void *buf,
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int size)
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{
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struct mt7620_sysc_priv *priv = dev_get_priv(dev);
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u32 val;
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if (offset % sizeof(u32) || size != sizeof(u32) ||
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offset >= SYSCTL_SIZE)
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return -EINVAL;
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val = readl(priv->base + offset);
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if (buf)
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*(u32 *)buf = val;
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return 0;
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}
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static int mt7620_sysc_write(struct udevice *dev, int offset, const void *buf,
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int size)
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{
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struct mt7620_sysc_priv *priv = dev_get_priv(dev);
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u32 val;
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if (offset % sizeof(u32) || size != sizeof(u32) ||
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offset >= SYSCTL_SIZE || !buf)
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return -EINVAL;
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val = *(u32 *)buf;
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writel(val, priv->base + offset);
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return 0;
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}
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static int mt7620_sysc_ioctl(struct udevice *dev, unsigned long request,
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void *buf)
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{
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struct mt7620_sysc_priv *priv = dev_get_priv(dev);
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struct mt7620_sysc_chip_rev *chip_rev;
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struct mt7620_sysc_clks *clks;
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u32 val, shift;
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if (!buf)
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return -EINVAL;
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switch (request) {
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case MT7620_SYSC_IOCTL_GET_CLK:
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clks = buf;
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mt7620_get_clks(&clks->cpu_clk, &clks->sys_clk,
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&clks->xtal_clk);
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val = readl(priv->base + SYSCTL_CLKCFG0_REG);
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if (val & PERI_CLK_SEL)
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clks->peri_clk = clks->xtal_clk;
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else
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clks->peri_clk = 40000000;
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return 0;
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case MT7620_SYSC_IOCTL_GET_CHIP_REV:
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chip_rev = buf;
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val = readl(priv->base + SYSCTL_CHIP_REV_ID_REG);
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chip_rev->bga = !!(val & PKG_ID);
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chip_rev->ver = (val & VER_M) >> VER_S;
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chip_rev->eco = (val & ECO_M) >> ECO_S;
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return 0;
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case MT7620_SYSC_IOCTL_SET_GE1_MODE:
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case MT7620_SYSC_IOCTL_SET_GE2_MODE:
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val = *(u32 *)buf;
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if (val > MT7620_SYSC_GE_ESW_PHY)
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return -EINVAL;
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if (request == MT7620_SYSC_IOCTL_SET_GE1_MODE)
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shift = GE1_MODE_S;
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else
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shift = GE2_MODE_S;
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clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG,
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GE_MODE_M << shift, val << shift);
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return 0;
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case MT7620_SYSC_IOCTL_SET_USB_MODE:
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val = *(u32 *)buf;
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if (val == MT7620_SYSC_USB_DEVICE_MODE)
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val = 0;
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else if (val == MT7620_SYSC_USB_HOST_MODE)
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val = USB0_HOST_MODE;
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clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG,
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USB0_HOST_MODE, val);
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return 0;
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case MT7620_SYSC_IOCTL_SET_PCIE_MODE:
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val = *(u32 *)buf;
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if (val == MT7620_SYSC_PCIE_EP_MODE)
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val = 0;
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else if (val == MT7620_SYSC_PCIE_RC_MODE)
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val = PCIE_RC_MODE;
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clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG,
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PCIE_RC_MODE, val);
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return 0;
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default:
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return -EINVAL;
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}
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}
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static int mt7620_sysc_probe(struct udevice *dev)
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{
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struct mt7620_sysc_priv *priv = dev_get_priv(dev);
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priv->base = dev_remap_addr_index(dev, 0);
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if (!priv->base) {
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dev_err(dev, "failed to map sysc registers\n");
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return -EINVAL;
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}
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return 0;
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}
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static struct misc_ops mt7620_sysc_ops = {
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.read = mt7620_sysc_read,
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.write = mt7620_sysc_write,
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.ioctl = mt7620_sysc_ioctl,
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};
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static const struct udevice_id mt7620_sysc_ids[] = {
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{ .compatible = "mediatek,mt7620-sysc" },
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{ }
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};
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U_BOOT_DRIVER(mt7620_sysc) = {
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.name = "mt7620_sysc",
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.id = UCLASS_MISC,
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.of_match = mt7620_sysc_ids,
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.probe = mt7620_sysc_probe,
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.ops = &mt7620_sysc_ops,
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.priv_auto = sizeof(struct mt7620_sysc_priv),
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.flags = DM_FLAG_PRE_RELOC,
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};
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