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![Chris Packham](/assets/img/avatar_default.png)
Bring in the Armada 370/XP dts/dtsi files from Linux. As U-Boot hasn't got the new NAND driver the updating binding has not been included. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
228 lines
4.8 KiB
Plaintext
228 lines
4.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell Armada XP development board
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* (DB-MV784MP-GP)
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*
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* Copyright (C) 2013-2014 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* Note: this Device Tree assumes that the bootloader has remapped the
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* internal registers to 0xf1000000 (instead of the default
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* 0xd0000000). The 0xf1000000 is the default used by the recent,
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* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
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* boards were delivered with an older version of the bootloader that
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* left internal registers mapped at 0xd0000000. If you are in this
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* situation, you should either update your bootloader (preferred
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* solution) or the below Device Tree should be adjusted.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-xp-mv78460.dtsi"
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/ {
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model = "Marvell Armada XP Development Board DB-MV784MP-GP";
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compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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/*
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* 8 GB of plug-in RAM modules by default.The amount
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* of memory available can be changed by the
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* bootloader according the size of the module
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* actually plugged. However, memory between
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* 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
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* the address range used for I/O (internal registers,
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* MBus windows).
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*/
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reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
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<0x00000001 0x00000000 0x00000001 0x00000000>;
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};
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cpus {
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pm_pic {
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ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
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<&gpio0 17 GPIO_ACTIVE_LOW>,
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<&gpio0 18 GPIO_ACTIVE_LOW>;
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};
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
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devbus-bootcs {
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status = "okay";
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/* Device Bus parameters are required */
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/* Read parameters */
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devbus,bus-width = <16>;
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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/* NOR 16 MiB */
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nor@0 {
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compatible = "cfi-flash";
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reg = <0 0x1000000>;
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bank-width = <2>;
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};
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};
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internal-regs {
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serial@12000 {
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status = "okay";
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};
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serial@12100 {
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status = "okay";
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};
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serial@12200 {
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status = "okay";
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};
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serial@12300 {
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status = "okay";
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};
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pinctrl {
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pinctrl-0 = <&pic_pins>;
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pinctrl-names = "default";
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pic_pins: pic-pins-0 {
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marvell,pins = "mpp16", "mpp17",
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"mpp18";
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marvell,function = "gpio";
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};
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};
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sata@a0000 {
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nr-ports = <2>;
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status = "okay";
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "qsgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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};
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ethernet@74000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "qsgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <1>;
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};
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ethernet@30000 {
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status = "okay";
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phy = <&phy2>;
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phy-mode = "qsgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <2>;
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};
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ethernet@34000 {
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status = "okay";
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phy = <&phy3>;
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phy-mode = "qsgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <3>;
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};
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/* Front-side USB slot */
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usb@50000 {
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status = "okay";
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};
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/* Back-side USB slot */
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usb@51000 {
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status = "okay";
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};
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bm@c0000 {
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status = "okay";
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};
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nand@d0000 {
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status = "okay";
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label = "pxa3xx_nand-0";
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num-cs = <1>;
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marvell,nand-keep-config;
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nand-on-flash-bbt;
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};
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};
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bm-bppi {
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status = "okay";
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};
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};
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};
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&pciec {
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status = "okay";
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/*
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* The 3 slots are physically present as
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@a,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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&mdio {
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phy0: ethernet-phy@0 {
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reg = <16>;
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};
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phy1: ethernet-phy@1 {
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reg = <17>;
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};
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phy2: ethernet-phy@2 {
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reg = <18>;
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};
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phy3: ethernet-phy@3 {
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reg = <19>;
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};
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};
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&spi0 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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