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https://github.com/brain-hackers/u-boot-brain
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76466bd7be
At the moment, the clk driver is not clever enough to automatically enable parent clocks like Linux. Enable the STDMAC clock explicitly if USB is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
77 lines
2.8 KiB
C
77 lines
2.8 KiB
C
/*
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* UniPhier SC (System Control) block registers for ARMv8 SoCs
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*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef SC64_REGS_H
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#define SC64_REGS_H
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#define SC_BASE_ADDR 0x61840000
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/* PLL type: SSC */
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#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */
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#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */
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#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */
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#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */
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#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */
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#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */
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#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */
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#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */
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#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */
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#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */
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#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */
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/* PLL type: VPLL27 */
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#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
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#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
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/* PLL type: DSPLL */
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#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
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#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
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#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
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#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
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#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
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#define SC_RSTCTRL4_ETHER (1 << 6)
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#define SC_RSTCTRL4_NAND (1 << 0)
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#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
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#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
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#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
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#define SC_RSTCTRL7_UMCSB (1 << 16)
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#define SC_RSTCTRL7_UMCA2 (1 << 10)
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#define SC_RSTCTRL7_UMCA1 (1 << 9)
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#define SC_RSTCTRL7_UMCA0 (1 << 8)
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#define SC_RSTCTRL7_UMC32 (1 << 2)
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#define SC_RSTCTRL7_UMC31 (1 << 1)
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#define SC_RSTCTRL7_UMC30 (1 << 0)
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#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
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#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
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#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
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#define SC_CLKCTRL4_MIO (1 << 10)
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#define SC_CLKCTRL4_STDMAC (1 << 8)
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#define SC_CLKCTRL4_PERI (1 << 7)
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#define SC_CLKCTRL4_ETHER (1 << 6)
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#define SC_CLKCTRL4_NAND (1 << 0)
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#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110)
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#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114)
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#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118)
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#define SC_CLKCTRL7_UMCSB (1 << 16)
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#define SC_CLKCTRL7_UMC32 (1 << 2)
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#define SC_CLKCTRL7_UMC31 (1 << 1)
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#define SC_CLKCTRL7_UMC30 (1 << 0)
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#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000)
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#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)
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#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008)
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#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080)
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#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084)
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#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)
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#define SC_CA_GEARUPD (1 << 0)
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#endif /* SC64_REGS_H */
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