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![Chunfeng Yun](/assets/img/avatar_default.png)
This patch adds support for the MediaTek USB3 DRD controller, its host side is based on xHCI, this driver supports device mode and host mode. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
506 lines
13 KiB
C
506 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* mtu3_qmu.c - Queue Management Unit driver for device controller
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*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
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*/
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/*
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* Queue Management Unit (QMU) is designed to unload SW effort
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* to serve DMA interrupts.
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* By preparing General Purpose Descriptor (GPD) and Buffer Descriptor (BD),
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* SW links data buffers and triggers QMU to send / receive data to
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* host / from device at a time.
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* And now only GPD is supported.
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*
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* For more detailed information, please refer to QMU Programming Guide
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*/
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#include <asm/cache.h>
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#include <cpu_func.h>
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#include <linux/iopoll.h>
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#include <linux/types.h>
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#include "mtu3.h"
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#define QMU_CHECKSUM_LEN 16
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#define GPD_FLAGS_HWO BIT(0)
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#define GPD_FLAGS_BDP BIT(1)
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#define GPD_FLAGS_BPS BIT(2)
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#define GPD_FLAGS_IOC BIT(7)
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#define GPD_EXT_FLAG_ZLP BIT(5)
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#define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
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void mtu3_flush_cache(uintptr_t addr, u32 len)
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{
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WARN_ON(!(void *)addr || len == 0);
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flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1),
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ALIGN(addr + len, DCACHELINE_SIZE));
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}
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void mtu3_inval_cache(uintptr_t addr, u32 len)
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{
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WARN_ON(!(void *)addr || len == 0);
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invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1),
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ALIGN(addr + len, DCACHELINE_SIZE));
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}
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static struct qmu_gpd *gpd_dma_to_virt(struct mtu3_gpd_ring *ring,
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dma_addr_t dma_addr)
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{
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dma_addr_t dma_base = ring->dma;
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struct qmu_gpd *gpd_head = ring->start;
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u32 offset = (dma_addr - dma_base) / sizeof(*gpd_head);
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if (offset >= MAX_GPD_NUM)
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return NULL;
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return gpd_head + offset;
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}
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static dma_addr_t gpd_virt_to_dma(struct mtu3_gpd_ring *ring,
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struct qmu_gpd *gpd)
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{
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dma_addr_t dma_base = ring->dma;
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struct qmu_gpd *gpd_head = ring->start;
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u32 offset;
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offset = gpd - gpd_head;
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if (offset >= MAX_GPD_NUM)
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return 0;
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return dma_base + (offset * sizeof(*gpd));
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}
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static void gpd_ring_init(struct mtu3_gpd_ring *ring, struct qmu_gpd *gpd)
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{
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ring->start = gpd;
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ring->enqueue = gpd;
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ring->dequeue = gpd;
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ring->end = gpd + MAX_GPD_NUM - 1;
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}
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static void reset_gpd_list(struct mtu3_ep *mep)
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{
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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struct qmu_gpd *gpd = ring->start;
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if (gpd) {
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gpd->flag &= ~GPD_FLAGS_HWO;
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gpd_ring_init(ring, gpd);
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mtu3_flush_cache((uintptr_t)gpd, sizeof(*gpd));
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}
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}
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int mtu3_gpd_ring_alloc(struct mtu3_ep *mep)
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{
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struct qmu_gpd *gpd;
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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/* software own all gpds as default */
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gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE);
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if (!gpd)
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return -ENOMEM;
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memset(gpd, 0, QMU_GPD_RING_SIZE);
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ring->dma = (dma_addr_t)gpd;
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gpd_ring_init(ring, gpd);
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return 0;
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}
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void mtu3_gpd_ring_free(struct mtu3_ep *mep)
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{
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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kfree(ring->start);
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memset(ring, 0, sizeof(*ring));
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}
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void mtu3_qmu_resume(struct mtu3_ep *mep)
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{
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struct mtu3 *mtu = mep->mtu;
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void __iomem *mbase = mtu->mac_base;
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int epnum = mep->epnum;
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u32 offset;
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offset = mep->is_in ? USB_QMU_TQCSR(epnum) : USB_QMU_RQCSR(epnum);
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mtu3_writel(mbase, offset, QMU_Q_RESUME);
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if (!(mtu3_readl(mbase, offset) & QMU_Q_ACTIVE))
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mtu3_writel(mbase, offset, QMU_Q_RESUME);
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}
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static struct qmu_gpd *advance_enq_gpd(struct mtu3_gpd_ring *ring)
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{
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if (ring->enqueue < ring->end)
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ring->enqueue++;
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else
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ring->enqueue = ring->start;
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return ring->enqueue;
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}
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static struct qmu_gpd *advance_deq_gpd(struct mtu3_gpd_ring *ring)
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{
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if (ring->dequeue < ring->end)
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ring->dequeue++;
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else
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ring->dequeue = ring->start;
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return ring->dequeue;
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}
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/* check if a ring is emtpy */
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static int gpd_ring_empty(struct mtu3_gpd_ring *ring)
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{
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struct qmu_gpd *enq = ring->enqueue;
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struct qmu_gpd *next;
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if (ring->enqueue < ring->end)
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next = enq + 1;
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else
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next = ring->start;
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/* one gpd is reserved to simplify gpd preparation */
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return next == ring->dequeue;
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}
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int mtu3_prepare_transfer(struct mtu3_ep *mep)
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{
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return gpd_ring_empty(&mep->gpd_ring);
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}
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static int mtu3_prepare_tx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
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{
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struct qmu_gpd *enq;
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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struct qmu_gpd *gpd = ring->enqueue;
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struct usb_request *req = &mreq->request;
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/* set all fields to zero as default value */
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memset(gpd, 0, sizeof(*gpd));
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gpd->buffer = cpu_to_le32((u32)req->dma);
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gpd->buf_len = cpu_to_le16(req->length);
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/* get the next GPD */
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enq = advance_enq_gpd(ring);
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dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p\n",
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mep->epnum, gpd, enq);
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enq->flag &= ~GPD_FLAGS_HWO;
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gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
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if (req->zero)
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gpd->ext_flag |= GPD_EXT_FLAG_ZLP;
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gpd->flag |= GPD_FLAGS_IOC | GPD_FLAGS_HWO;
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mreq->gpd = gpd;
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if (req->length)
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mtu3_flush_cache((uintptr_t)req->buf, req->length);
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mtu3_flush_cache((uintptr_t)gpd, sizeof(*gpd));
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return 0;
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}
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static int mtu3_prepare_rx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
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{
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struct qmu_gpd *enq;
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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struct qmu_gpd *gpd = ring->enqueue;
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struct usb_request *req = &mreq->request;
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/* set all fields to zero as default value */
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memset(gpd, 0, sizeof(*gpd));
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gpd->buffer = cpu_to_le32((u32)req->dma);
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gpd->data_buf_len = cpu_to_le16(req->length);
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/* get the next GPD */
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enq = advance_enq_gpd(ring);
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dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p\n",
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mep->epnum, gpd, enq);
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enq->flag &= ~GPD_FLAGS_HWO;
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gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
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gpd->flag |= GPD_FLAGS_IOC | GPD_FLAGS_HWO;
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mreq->gpd = gpd;
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mtu3_inval_cache((uintptr_t)req->buf, req->length);
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mtu3_flush_cache((uintptr_t)gpd, sizeof(*gpd));
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return 0;
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}
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void mtu3_insert_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
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{
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if (mep->is_in)
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mtu3_prepare_tx_gpd(mep, mreq);
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else
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mtu3_prepare_rx_gpd(mep, mreq);
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}
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int mtu3_qmu_start(struct mtu3_ep *mep)
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{
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struct mtu3 *mtu = mep->mtu;
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void __iomem *mbase = mtu->mac_base;
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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u8 epnum = mep->epnum;
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if (mep->is_in) {
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/* set QMU start address */
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mtu3_writel(mbase, USB_QMU_TQSAR(epnum), ring->dma);
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mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_DMAREQEN);
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/* send zero length packet according to ZLP flag in GPD */
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mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum));
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mtu3_writel(mbase, U3D_TQERRIESR0,
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QMU_TX_LEN_ERR(epnum) | QMU_TX_CS_ERR(epnum));
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if (mtu3_readl(mbase, USB_QMU_TQCSR(epnum)) & QMU_Q_ACTIVE) {
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dev_warn(mtu->dev, "Tx %d Active Now!\n", epnum);
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return 0;
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}
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mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START);
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} else {
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mtu3_writel(mbase, USB_QMU_RQSAR(epnum), ring->dma);
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mtu3_setbits(mbase, MU3D_EP_RXCR0(epnum), RX_DMAREQEN);
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/* don't expect ZLP */
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mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum));
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/* move to next GPD when receive ZLP */
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mtu3_setbits(mbase, U3D_QCR3, QMU_RX_COZ(epnum));
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mtu3_writel(mbase, U3D_RQERRIESR0,
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QMU_RX_LEN_ERR(epnum) | QMU_RX_CS_ERR(epnum));
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mtu3_writel(mbase, U3D_RQERRIESR1, QMU_RX_ZLP_ERR(epnum));
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if (mtu3_readl(mbase, USB_QMU_RQCSR(epnum)) & QMU_Q_ACTIVE) {
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dev_warn(mtu->dev, "Rx %d Active Now!\n", epnum);
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return 0;
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}
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mtu3_writel(mbase, USB_QMU_RQCSR(epnum), QMU_Q_START);
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}
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return 0;
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}
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/* may called in atomic context */
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void mtu3_qmu_stop(struct mtu3_ep *mep)
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{
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struct mtu3 *mtu = mep->mtu;
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void __iomem *mbase = mtu->mac_base;
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int epnum = mep->epnum;
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u32 value = 0;
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u32 qcsr;
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int ret;
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qcsr = mep->is_in ? USB_QMU_TQCSR(epnum) : USB_QMU_RQCSR(epnum);
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if (!(mtu3_readl(mbase, qcsr) & QMU_Q_ACTIVE)) {
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dev_dbg(mtu->dev, "%s's qmu is inactive now!\n", mep->name);
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return;
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}
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mtu3_writel(mbase, qcsr, QMU_Q_STOP);
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ret = readl_poll_timeout(mbase + qcsr, value,
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!(value & QMU_Q_ACTIVE), 1000);
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if (ret) {
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dev_err(mtu->dev, "stop %s's qmu failed\n", mep->name);
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return;
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}
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dev_dbg(mtu->dev, "%s's qmu stop now!\n", mep->name);
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}
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void mtu3_qmu_flush(struct mtu3_ep *mep)
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{
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dev_dbg(mep->mtu->dev, "%s flush QMU %s\n", __func__,
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((mep->is_in) ? "TX" : "RX"));
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/*Stop QMU */
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mtu3_qmu_stop(mep);
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reset_gpd_list(mep);
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}
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/*
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* NOTE: request list maybe is already empty as following case:
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* queue_tx --> qmu_interrupt(clear interrupt pending, schedule tasklet)-->
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* queue_tx --> process_tasklet(meanwhile, the second one is transferred,
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* tasklet process both of them)-->qmu_interrupt for second one.
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* To avoid upper case, put qmu_done_tx in ISR directly to process it.
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*/
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static void qmu_done_tx(struct mtu3 *mtu, u8 epnum)
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{
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struct mtu3_ep *mep = mtu->in_eps + epnum;
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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void __iomem *mbase = mtu->mac_base;
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struct qmu_gpd *gpd = ring->dequeue;
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struct qmu_gpd *gpd_current = NULL;
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struct usb_request *req = NULL;
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struct mtu3_request *mreq;
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dma_addr_t cur_gpd_dma;
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/*transfer phy address got from QMU register to virtual address */
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cur_gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
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gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
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mtu3_inval_cache((uintptr_t)gpd, sizeof(*gpd));
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dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
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__func__, epnum, gpd, gpd_current, ring->enqueue);
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while (gpd != gpd_current && !(gpd->flag & GPD_FLAGS_HWO)) {
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mreq = next_request(mep);
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if (!mreq || mreq->gpd != gpd) {
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dev_err(mtu->dev, "no correct TX req is found\n");
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break;
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}
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req = &mreq->request;
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req->actual = le16_to_cpu(gpd->buf_len);
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mtu3_req_complete(mep, req, 0);
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gpd = advance_deq_gpd(ring);
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mtu3_inval_cache((uintptr_t)gpd, sizeof(*gpd));
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}
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dev_dbg(mtu->dev, "%s EP%d, deq=%p, enq=%p, complete\n",
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__func__, epnum, ring->dequeue, ring->enqueue);
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}
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static void qmu_done_rx(struct mtu3 *mtu, u8 epnum)
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{
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struct mtu3_ep *mep = mtu->out_eps + epnum;
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struct mtu3_gpd_ring *ring = &mep->gpd_ring;
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void __iomem *mbase = mtu->mac_base;
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struct qmu_gpd *gpd = ring->dequeue;
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struct qmu_gpd *gpd_current = NULL;
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struct usb_request *req = NULL;
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struct mtu3_request *mreq;
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dma_addr_t cur_gpd_dma;
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cur_gpd_dma = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
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gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
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mtu3_inval_cache((uintptr_t)gpd, sizeof(*gpd));
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dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
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__func__, epnum, gpd, gpd_current, ring->enqueue);
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while (gpd != gpd_current && !(gpd->flag & GPD_FLAGS_HWO)) {
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mreq = next_request(mep);
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if (!mreq || mreq->gpd != gpd) {
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dev_err(mtu->dev, "no correct RX req is found\n");
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break;
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}
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req = &mreq->request;
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req->actual = le16_to_cpu(gpd->buf_len);
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mtu3_req_complete(mep, req, 0);
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gpd = advance_deq_gpd(ring);
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mtu3_inval_cache((uintptr_t)gpd, sizeof(*gpd));
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}
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dev_dbg(mtu->dev, "%s EP%d, deq=%p, enq=%p, complete\n",
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__func__, epnum, ring->dequeue, ring->enqueue);
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}
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static void qmu_done_isr(struct mtu3 *mtu, u32 done_status)
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{
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int i;
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for (i = 1; i < mtu->num_eps; i++) {
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if (done_status & QMU_RX_DONE_INT(i))
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qmu_done_rx(mtu, i);
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if (done_status & QMU_TX_DONE_INT(i))
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qmu_done_tx(mtu, i);
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}
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}
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static void qmu_exception_isr(struct mtu3 *mtu, u32 qmu_status)
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{
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void __iomem *mbase = mtu->mac_base;
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u32 errval;
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int i;
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if ((qmu_status & RXQ_CSERR_INT) || (qmu_status & RXQ_LENERR_INT)) {
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errval = mtu3_readl(mbase, U3D_RQERRIR0);
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for (i = 1; i < mtu->num_eps; i++) {
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if (errval & QMU_RX_CS_ERR(i))
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dev_err(mtu->dev, "Rx %d CS error!\n", i);
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if (errval & QMU_RX_LEN_ERR(i))
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dev_err(mtu->dev, "RX %d Length error\n", i);
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}
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mtu3_writel(mbase, U3D_RQERRIR0, errval);
|
|
}
|
|
|
|
if (qmu_status & RXQ_ZLPERR_INT) {
|
|
errval = mtu3_readl(mbase, U3D_RQERRIR1);
|
|
for (i = 1; i < mtu->num_eps; i++) {
|
|
if (errval & QMU_RX_ZLP_ERR(i))
|
|
dev_dbg(mtu->dev, "RX EP%d Recv ZLP\n", i);
|
|
}
|
|
mtu3_writel(mbase, U3D_RQERRIR1, errval);
|
|
}
|
|
|
|
if ((qmu_status & TXQ_CSERR_INT) || (qmu_status & TXQ_LENERR_INT)) {
|
|
errval = mtu3_readl(mbase, U3D_TQERRIR0);
|
|
for (i = 1; i < mtu->num_eps; i++) {
|
|
if (errval & QMU_TX_CS_ERR(i))
|
|
dev_err(mtu->dev, "Tx %d checksum error!\n", i);
|
|
|
|
if (errval & QMU_TX_LEN_ERR(i))
|
|
dev_err(mtu->dev, "Tx %d zlp error!\n", i);
|
|
}
|
|
mtu3_writel(mbase, U3D_TQERRIR0, errval);
|
|
}
|
|
}
|
|
|
|
irqreturn_t mtu3_qmu_isr(struct mtu3 *mtu)
|
|
{
|
|
void __iomem *mbase = mtu->mac_base;
|
|
u32 qmu_status;
|
|
u32 qmu_done_status;
|
|
|
|
/* U3D_QISAR1 is read update */
|
|
qmu_status = mtu3_readl(mbase, U3D_QISAR1);
|
|
qmu_status &= mtu3_readl(mbase, U3D_QIER1);
|
|
|
|
qmu_done_status = mtu3_readl(mbase, U3D_QISAR0);
|
|
qmu_done_status &= mtu3_readl(mbase, U3D_QIER0);
|
|
mtu3_writel(mbase, U3D_QISAR0, qmu_done_status); /* W1C */
|
|
dev_dbg(mtu->dev, "=== QMUdone[tx=%x, rx=%x] QMUexp[%x] ===\n",
|
|
(qmu_done_status & 0xFFFF), qmu_done_status >> 16,
|
|
qmu_status);
|
|
|
|
if (qmu_done_status)
|
|
qmu_done_isr(mtu, qmu_done_status);
|
|
|
|
if (qmu_status)
|
|
qmu_exception_isr(mtu, qmu_status);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
void mtu3_qmu_init(struct mtu3 *mtu)
|
|
{
|
|
compiletime_assert(QMU_GPD_SIZE == 16, "QMU_GPD size SHOULD be 16B");
|
|
}
|
|
|
|
void mtu3_qmu_exit(struct mtu3 *mtu)
|
|
{
|
|
}
|