u-boot-brain/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h

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630 B
C

/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2018 Microsemi Corporation
*/
#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
#define _MSCC_OCELOT_DEVCPU_GCB_H_
#define PERF_SOFT_RST 0x8
#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
#define PERF_GPIO_OUT_SET 0x34
#define PERF_GPIO_OUT_CLR 0x38
#define PERF_GPIO_OE 0x44
#endif