25 lines
684 B
C
25 lines
684 B
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#ifndef __ASM_MACH_COMMON_H
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#define __ASM_MACH_COMMON_H
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#if defined(CONFIG_SOC_OCELOT)
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#include <mach/ocelot/ocelot.h>
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#include <mach/ocelot/ocelot_devcpu_gcb.h>
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#include <mach/ocelot/ocelot_icpu_cfg.h>
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#else
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#error Unsupported platform
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#endif
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#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */
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#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */
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#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */
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#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */
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#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */
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#endif /* __ASM_MACH_COMMON_H */
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