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https://github.com/brain-hackers/u-boot-brain
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96bda02c9e
T1040 has only one SerDes block. so update the code accordingly. Also, add support of SerDes Protocol 0x00, 0x06, 0x40, 0x69 0x85, 0xA7 and 0xAA Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
227 lines
5.5 KiB
C
227 lines
5.5 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/immap_85xx.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/fsl_law.h>
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#include <asm/errno.h>
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#include "fsl_corenet2_serdes.h"
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#ifdef CONFIG_SYS_FSL_SRDS_1
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static u64 serdes1_prtcl_map;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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static u64 serdes2_prtcl_map;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_3
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static u64 serdes3_prtcl_map;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_4
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static u64 serdes4_prtcl_map;
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#endif
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#ifdef DEBUG
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static const char *serdes_prtcl_str[] = {
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[NONE] = "NA",
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[PCIE1] = "PCIE1",
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[PCIE2] = "PCIE2",
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[PCIE3] = "PCIE3",
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[PCIE4] = "PCIE4",
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[SATA1] = "SATA1",
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[SATA2] = "SATA2",
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[SRIO1] = "SRIO1",
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[SRIO2] = "SRIO2",
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[SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
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[SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
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[SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
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[SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
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[SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
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[SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
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[SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
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[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
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[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
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[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
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[XAUI_FM1] = "XAUI_FM1",
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[XAUI_FM2] = "XAUI_FM2",
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[AURORA] = "DEBUG",
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[CPRI1] = "CPRI1",
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[CPRI2] = "CPRI2",
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[CPRI3] = "CPRI3",
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[CPRI4] = "CPRI4",
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[CPRI5] = "CPRI5",
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[CPRI6] = "CPRI6",
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[CPRI7] = "CPRI7",
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[CPRI8] = "CPRI8",
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[XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
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[XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
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[XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
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[XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
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[HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
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[HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
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[HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
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[HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
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[QSGMII_FM1_A] = "QSGMII_FM1_A",
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[QSGMII_FM1_B] = "QSGMII_FM1_B",
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[QSGMII_FM2_A] = "QSGMII_FM2_A",
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[QSGMII_FM2_B] = "QSGMII_FM2_B",
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[XFI_FM1_MAC9] = "XFI_FM1_MAC9",
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[XFI_FM1_MAC10] = "XFI_FM1_MAC10",
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[XFI_FM2_MAC9] = "XFI_FM2_MAC9",
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[XFI_FM2_MAC10] = "XFI_FM2_MAC10",
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[INTERLAKEN] = "INTERLAKEN",
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[QSGMII_SW1_A] = "QSGMII_SW1_A",
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[QSGMII_SW1_B] = "QSGMII_SW1_B",
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};
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#endif
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int is_serdes_configured(enum srds_prtcl device)
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{
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u64 ret = 0;
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#ifdef CONFIG_SYS_FSL_SRDS_1
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ret |= (1ULL << device) & serdes1_prtcl_map;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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ret |= (1ULL << device) & serdes2_prtcl_map;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_3
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ret |= (1ULL << device) & serdes3_prtcl_map;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_4
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ret |= (1ULL << device) & serdes4_prtcl_map;
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#endif
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return !!ret;
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}
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
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{
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const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 cfg = in_be32(&gur->rcwsr[4]);
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int i;
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switch (sd) {
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#ifdef CONFIG_SYS_FSL_SRDS_1
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case FSL_SRDS_1:
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cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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case FSL_SRDS_2:
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cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_3
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case FSL_SRDS_3:
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cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
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cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_4
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case FSL_SRDS_4:
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cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
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cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
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break;
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#endif
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default:
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printf("invalid SerDes%d\n", sd);
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break;
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}
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/* Is serdes enabled at all? */
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if (unlikely(cfg == 0))
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return -ENODEV;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_get_prtcl(sd, cfg, i) == device)
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return i;
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}
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return -ENODEV;
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}
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u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u64 serdes_prtcl_map = 0;
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u32 cfg;
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int lane;
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cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
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/* Is serdes enabled at all? */
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if (!cfg) {
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printf("SERDES%d is not enabled\n", sd + 1);
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return 0;
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}
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cfg >>= sd_prctl_shift;
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printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
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if (!is_serdes_prtcl_valid(sd, cfg))
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printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
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serdes_prtcl_map |= (1ULL << lane_prtcl);
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}
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return serdes_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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#ifdef CONFIG_SYS_FSL_SRDS_1
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serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
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CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
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CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_3
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serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
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CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
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FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
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FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_4
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serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
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CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
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FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
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FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
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#endif
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}
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const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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case SRDS_PLLCR0_RFCK_SEL_161_13:
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return "161.1328123";
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default:
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#if defined(CONFIG_T4240QDS)
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return "???";
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#else
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return "122.88";
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#endif
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}
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}
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