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![Stefano Babic](/assets/img/avatar_default.png)
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
72 lines
2.0 KiB
C
72 lines
2.0 KiB
C
/*
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* Freescale i.MXS Register Accessors
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MXS_REGS_COMMON_H__
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#define __MXS_REGS_COMMON_H__
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#include <linux/types.h>
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/*
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* The i.MXS has interesting feature when it comes to register access. There
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* are four kinds of access to one particular register. Those are:
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*
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* 1) Common read/write access. To use this mode, just write to the address of
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* the register.
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* 2) Set bits only access. To set bits, write which bits you want to set to the
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* address of the register + 0x4.
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* 3) Clear bits only access. To clear bits, write which bits you want to clear
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* to the address of the register + 0x8.
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* 4) Toggle bits only access. To toggle bits, write which bits you want to
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* toggle to the address of the register + 0xc.
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*
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* IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
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* can be set/cleared by pure write as in access type 1, some need to be
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* explicitly set/cleared by using access type 2-3.
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*
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* The following macros and structures allow the user to either access the
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* register in all aforementioned modes (by accessing reg_name, reg_name_set,
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* reg_name_clr, reg_name_tog) or pass the register structure further into
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* various functions with correct type information (by accessing reg_name_reg).
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*
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*/
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#define __mxs_reg_8(name) \
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uint8_t name[4]; \
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uint8_t name##_set[4]; \
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uint8_t name##_clr[4]; \
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uint8_t name##_tog[4]; \
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#define __mxs_reg_32(name) \
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uint32_t name; \
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uint32_t name##_set; \
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uint32_t name##_clr; \
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uint32_t name##_tog;
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struct mxs_register_8 {
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__mxs_reg_8(reg)
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};
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struct mxs_register_32 {
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__mxs_reg_32(reg)
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};
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#define mxs_reg_8(name) \
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union { \
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struct { __mxs_reg_8(name) }; \
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struct mxs_register_8 name##_reg; \
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};
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#define mxs_reg_32(name) \
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union { \
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struct { __mxs_reg_32(name) }; \
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struct mxs_register_32 name##_reg; \
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};
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#endif /* __MXS_REGS_COMMON_H__ */
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