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![Sriram Dash](/assets/img/avatar_default.png)
IFC code is put under CONFIG_FSL_IFC Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
374 lines
13 KiB
C
374 lines
13 KiB
C
/*
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* Copyright 2017 NXP
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* Copyright 2014-2015, Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _FSL_LAYERSCAPE_CPU_H
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#define _FSL_LAYERSCAPE_CPU_H
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static struct cpu_type cpu_type_list[] = {
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CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
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CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
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CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
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CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
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CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
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CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
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CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
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CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
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CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
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CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
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CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
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CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
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CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
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CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
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CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
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CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
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CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
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CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
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CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
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};
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#ifndef CONFIG_SYS_DCACHE_OFF
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#ifdef CONFIG_FSL_LSCH3
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#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
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#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
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#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
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#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
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#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
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#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
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#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
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#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
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#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
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#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
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#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
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#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
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#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
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#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
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#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
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#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
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#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
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#define CONFIG_SYS_FSL_NI_BASE 0x810000000
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#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
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#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
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#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
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#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
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#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
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#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
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#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
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#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
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#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
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#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
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#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
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#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
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#elif defined(CONFIG_FSL_LSCH2)
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#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
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#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
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#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
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#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
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#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
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#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
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#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
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#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
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#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
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#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
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#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
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#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
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#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
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#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
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#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
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#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
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#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
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#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
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#endif
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#define EARLY_PGTABLE_SIZE 0x5000
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static struct mm_region early_map[] = {
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#ifdef CONFIG_FSL_LSCH3
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
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CONFIG_SYS_FSL_CCSR_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
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SYS_FSL_OCRAM_SPACE_SIZE,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
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},
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{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
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CONFIG_SYS_FSL_QSPI_SIZE1,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
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#ifdef CONFIG_FSL_IFC
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/* For IFC Region #1, only the first 4MB is cache-enabled */
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{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
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CONFIG_SYS_FSL_IFC_SIZE1_1,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
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},
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{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
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CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
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CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
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},
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{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
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CONFIG_SYS_FSL_IFC_SIZE1,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
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},
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#endif
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
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CONFIG_SYS_FSL_DRAM_SIZE1,
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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#endif
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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#ifdef CONFIG_FSL_IFC
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/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
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{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
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CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
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},
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#endif
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
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CONFIG_SYS_FSL_DCSR_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
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CONFIG_SYS_FSL_DRAM_SIZE2,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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#elif defined(CONFIG_FSL_LSCH2)
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
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CONFIG_SYS_FSL_CCSR_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
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SYS_FSL_OCRAM_SPACE_SIZE,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
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},
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
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CONFIG_SYS_FSL_DCSR_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
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CONFIG_SYS_FSL_QSPI_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
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},
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#ifdef CONFIG_FSL_IFC
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{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
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CONFIG_SYS_FSL_IFC_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
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},
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#endif
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
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CONFIG_SYS_FSL_DRAM_SIZE1,
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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#endif
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
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CONFIG_SYS_FSL_DRAM_SIZE2,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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#endif
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{}, /* list terminator */
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};
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static struct mm_region final_map[] = {
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#ifdef CONFIG_FSL_LSCH3
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
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CONFIG_SYS_FSL_CCSR_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
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SYS_FSL_OCRAM_SPACE_SIZE,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
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},
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
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CONFIG_SYS_FSL_DRAM_SIZE1,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
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CONFIG_SYS_FSL_QSPI_SIZE1,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
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CONFIG_SYS_FSL_QSPI_SIZE2,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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#ifdef CONFIG_FSL_IFC
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{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
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CONFIG_SYS_FSL_IFC_SIZE2,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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#endif
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
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CONFIG_SYS_FSL_DCSR_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
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CONFIG_SYS_FSL_MC_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
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CONFIG_SYS_FSL_NI_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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/* For QBMAN portal, only the first 64MB is cache-enabled */
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{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
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CONFIG_SYS_FSL_QBMAN_SIZE_1,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
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},
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{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
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CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
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CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
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CONFIG_SYS_PCIE1_PHYS_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
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CONFIG_SYS_PCIE2_PHYS_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
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CONFIG_SYS_PCIE3_PHYS_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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#ifdef CONFIG_ARCH_LS2080A
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{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
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CONFIG_SYS_PCIE4_PHYS_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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#endif
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{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
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CONFIG_SYS_FSL_WRIOP1_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
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CONFIG_SYS_FSL_AIOP1_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
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CONFIG_SYS_FSL_PEBUF_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
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CONFIG_SYS_FSL_DRAM_SIZE2,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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#elif defined(CONFIG_FSL_LSCH2)
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{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
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CONFIG_SYS_FSL_BOOTROM_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
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CONFIG_SYS_FSL_CCSR_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
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SYS_FSL_OCRAM_SPACE_SIZE,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
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},
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{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
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CONFIG_SYS_FSL_DCSR_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
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CONFIG_SYS_FSL_QSPI_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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#ifdef CONFIG_FSL_IFC
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{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
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CONFIG_SYS_FSL_IFC_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
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},
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#endif
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
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CONFIG_SYS_FSL_DRAM_SIZE1,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
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CONFIG_SYS_FSL_QBMAN_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
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CONFIG_SYS_FSL_DRAM_SIZE2,
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|
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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|
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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|
},
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|
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
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|
CONFIG_SYS_PCIE1_PHYS_SIZE,
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|
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
},
|
|
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
|
|
CONFIG_SYS_PCIE2_PHYS_SIZE,
|
|
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
},
|
|
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
|
|
CONFIG_SYS_PCIE3_PHYS_SIZE,
|
|
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
},
|
|
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
|
|
CONFIG_SYS_FSL_DRAM_SIZE3,
|
|
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
|
{}, /* space holder for secure mem */
|
|
#endif
|
|
{},
|
|
};
|
|
#endif /* !CONFIG_SYS_DCACHE_OFF */
|
|
|
|
int fsl_qoriq_core_to_cluster(unsigned int core);
|
|
u32 cpu_mask(void);
|
|
|
|
#endif /* _FSL_LAYERSCAPE_CPU_H */
|